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CY23FS04ZXCT

更新时间: 2024-11-18 03:02:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 215K
描述
Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer

CY23FS04ZXCT 数据手册

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CY23FS04  
Failsafe™ 2.5V/ 3.3V Zero Delay Buffer  
Features  
Functional Description  
• Internal DCXO for continuous glitch-free operation  
• Zero input-output propagation delay  
• Low-jitter (< 35 ps RMS) outputs  
• Low Output-to-Output skew (< 200 ps)  
• 4.17 MHz–170 MHz reference input  
• Supports industry standard input crystals  
• 170 MHz outputs  
The CY23FS04 is a FailSafezero delay buffer with two  
reference clock inputs and four phase-aligned outputs. The  
device provides an optimum solution for applications where  
continuous operation is required in the event of a primary clock  
failure.  
The continuous, glitch-free operation is achieved by using a  
DCXO, which serves as a redundant clock source in the event  
of a reference clock failure by maintaining the last frequency  
and phase information of the reference clock.  
• 5V-tolerant inputs  
• Phase-locked loop (PLL) Bypass Mode  
• Dual Reference Inputs  
The unique feature of the CY23FS04 is that the DCXO is in  
fact the primary clocking source, which is synchronized  
(phase-aligned) to the external reference clock. When this  
external clock is restored, the DCXO automatically resynchro-  
nizes to the external clock.  
• 16-pin TSSOP  
The frequency of the crystal, which will be connected to the  
DCXO must be chosen to be an integer factor of the frequency  
of the reference clock. This factor is set by two select lines:  
S[2:1], please see Table 1. Output power supply, VDD can be  
connected to either 2.5V or 3.3V. VDDC is the power supply  
pin for internal circuits and must be connected to 3.3V.  
• 2.5V or 3.3V output power supplies  
• 3.3V core power supply  
• Industrial temperature available  
Block Diagram  
Pin Configuration  
XIN XOUT  
REF1  
REF2  
CLKB1  
CLKB2  
S2  
VSS  
VDDC  
XIN  
REFSEL  
FBK  
CLKA1  
CLKA2  
S1  
VDD  
FAIL#/SAFE  
XOUT  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
REFSEL  
DCXO  
REF1  
2
2
CLKA[1:2]  
CLKB[1:2]  
FailsafeTM  
REF2  
FBK  
PLL  
Block  
16 pin TSSOP  
Decoder  
FAIL# /SAFE  
2
S[2:1]  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07304 Rev. *C  
Revised June 8, 2005  

CY23FS04ZXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY23FS04ZXC CYPRESS

完全替代

Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXIT CYPRESS

类似代替

Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS04ZXI CYPRESS

类似代替

Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer

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