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CY23S02-01SC PDF预览

CY23S02-01SC

更新时间: 2024-11-05 22:50:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管倍频器
页数 文件大小 规格书
7页 106K
描述
Spread Aware, Frequency Multiplier and Zero Delay Buffer

CY23S02-01SC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, SOIC-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.8其他特性:4.5V TO 5.5V SUPPLY VOLTAGE ALSO AVAILABLE
系列:23S输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):220
传播延迟(tpd):0.35 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

CY23S02-01SC 数据手册

 浏览型号CY23S02-01SC的Datasheet PDF文件第2页浏览型号CY23S02-01SC的Datasheet PDF文件第3页浏览型号CY23S02-01SC的Datasheet PDF文件第4页浏览型号CY23S02-01SC的Datasheet PDF文件第5页浏览型号CY23S02-01SC的Datasheet PDF文件第6页浏览型号CY23S02-01SC的Datasheet PDF文件第7页 
02  
CY23S02  
Spread Aware™, Frequency Multiplier and Zero Delay Buffer  
Table 1. Configuration Options  
Features  
FBIN  
OUT1  
OUT1  
OUT1  
OUT1  
OUT2  
OUT2  
OUT2  
OUT2  
FS0  
0
FS1  
0
OUT1  
2 X REF  
4 X REF  
REF  
OUT2  
REF  
• Spread Aware™—designed to work with SSFTG  
reference signals  
• Two outputs  
• Configuration options allow various multiplication of  
the reference frequency, refer to Table 1 to determine  
the specific option which meets your multiplication  
needs  
1
0
2 X REF  
REF/2  
0
1
1
1
8 X REF  
4 X REF  
8 X REF  
2 X REF  
16 X REF  
4 X REF  
2 X REF  
4 X REF  
REF  
0
0
• Available in 8-pin SOIC package  
1
0
Key Specifications  
0
1
Operating Voltage: ..........................3.3V ±5% or 5.0V ±10%  
Operating Range: ......................20 MHz < fOUT1 < 133 MHz  
Absolute Jitter: ......................................................... ±500 ps  
Output to Output Skew: ............................................. 250 ps  
1
1
8 X REF  
Propagation Delay: ................................................... ±350 ps  
Propagation delay is affected by input rise time.  
Block Diagram  
Pin Configuration  
External feedback connection to  
OUT1 or OUT2, not both  
FBIN  
FBIN  
IN  
1
2
3
4
8
7
6
5
OUT2  
VDD  
OUT1  
FS1  
GND  
FS0  
FS0  
÷Q  
FS1  
Phase  
Detector  
Charge  
Pump  
IN  
Reference  
Input  
Loop  
Filter  
Output  
Buffer  
OUT1  
OUT2  
VCO  
Output  
Buffer  
÷2  
Spread Aware is a trademark of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07155 Rev. **  
Revised September 25, 2001  

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