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CY23FS08OXC

更新时间: 2024-11-06 03:12:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 271K
描述
Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer

CY23FS08OXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP,
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.75JESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
湿度敏感等级:3端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:30 MHz认证状态:Not Qualified
座面最大高度:2 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY23FS08OXC 数据手册

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CY23FS08  
Failsafe™ 2.5V/ 3.3V Zero Delay Buffer  
Features  
Functional Description  
• Internal DCXO for continuous glitch-free operation  
• Zero input-output propagation delay  
• 100ps typical output cycle-to-cycle jitter  
• 110 ps typical Output-output skew  
• 1 MHz–200 MHz reference input  
• Supports industry standard input crystals  
• 200 MHz (commercial), 166 MHz (industrial) outputs  
• 5V-tolerant inputs  
The CY23FS08 is a FailSafe™ Zero Delay Buffer with two  
reference clock inputs and eight phase-aligned outputs. The  
device provides an optimum solution for applications where  
continuous operation is required in the event of a primary clock  
failure.  
Continuous, glitch-free operation is achieved by using a  
DCXO, which serves as a redundant clock source in the event  
of a reference clock failure by maintaining the last frequency  
and phase information of the reference clock.  
The unique feature of the CY23FS08 is that the DCXO is in  
fact the primary clocking source, which is synchronized  
(phase-aligned) to the external reference clock. When this  
external clock is restored, the DCXO automatically resynchro-  
nizes to the external clock.  
• Phase-locked loop (PLL) Bypass Mode  
• Dual Reference Inputs  
• 28-pin SSOP  
The frequency of the crystal, which will be connected to the  
DCXO must be chosen to be an integer factor of the frequency  
of the reference clock. This factor is set by four select lines:  
S[4:1]. please see Table 1. The CY23FS08 has three split  
power supplies; one for core, another for Bank A outputs and  
the third for Bank B outputs. Each output power supply, except  
VDDC can be connected to either 2.5V or 3.3V. VDDC is the  
power supply pin for internal circuits and must be connected  
to 3.3V.  
• Split 2.5V or 3.3V output power supplies  
• 3.3V core power supply  
• Industrial temperature available  
Block Diagram  
Pin Configuration  
XIN XOUT  
REF1  
REF2  
VSSB  
CLKB1  
CLKB2  
S2  
REFSEL  
FBK  
28  
27  
26  
25  
24  
23  
22  
21  
REFSEL  
DCXO  
1
2
3
4
5
6
7
8
VSSA  
CLKA1  
CLKA2  
S1  
REF1  
4
4
CLKA[1:4]  
CLKB[1:4]  
FailsafeTM  
Block  
REF2  
FBK  
PLL  
S3  
S4  
VDDB  
VDDA  
VSSB  
CLKB3  
CLKB4  
VDDB  
VDDC  
XIN  
9
VSSA  
20  
19  
18  
17  
16  
15  
10  
11  
12  
13  
14  
CLKA3  
CLKA4  
VDDA  
Decoder  
FAIL# /SAFE  
4
S[4:1]  
FAIL#/SAFE  
XOUT  
28-pin SSOP  
Cypress Semiconductor Corporation  
Document #: 38-07518 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 2, 2006  

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