CY23FS08

更新时间： 2024-09-15 23:13:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	239K
描述
Failsafe 2.5V/ 3.3V Zero Delay Buffer

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中文翻译

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CY23FS08 数据手册

CY23FS08

Failsafe™ 2.5V/ 3.3V Zero Delay Buffer

Features

Functional Description

• Internal DCXO for continuous glitch-free operation

• Zero input-output propagation delay

• Low jitter (< 35 ps RMS) outputs

• Low output-output skew (< 200 ps)

• 1 MHz–200 MHz reference input

• Supports industry standard input crystals

• 200 MHz (commercial), 166 MHz (industrial) outputs

• 5V-tolerant inputs

• Phase-locked loop (PLL) Bypass Mode

• Dual Reference Inputs

• 28-pin SSOP

• Split 2.5V or 3.3V output power supplies

• 3.3V core power supply

• Industrial temperature available

The CY23FS08 is a FailSafe^™Zero Delay Buffer with two

reference clock inputs and eight phase-aligned outputs. The

device provides an optimum solution for applications where

continuous operation is required in the event of a primary clock

failure.

Continuous, glitch-free operation is achieved by using a

DCXO, which serves as a redundant clock source in the event

of a reference clock failure by maintaining the last frequency

and phase information of the reference clock.

The unique feature of the CY23FS08 is that the DCXO is in

fact the primary clocking source, which is synchronized

(phase-aligned) to the external reference clock. When this

external clock is restored, the DCXO automatically resynchro-

nizes to the external clock.

The frequency of the crystal, which will be connected to the

DCXO must be chosen to be an integer factor of the frequency

of the reference clock. This factor is set by four select lines:

S[4:1]. please see Table 1. The CY23FS08 has three split

power supplies; one for core, another for Bank A outputs and

the third for Bank B outputs. Each output power supply, except

VDDC can be connected to either 2.5V or 3.3V. VDDC is the

power supply pin for internal circuits and must be connected

to 3.3V.

Block Diagram

Pin Configuration

XIN XOUT

REF1

REF2

VSSB

CLKB1

CLKB2

REFSEL

FBK

VSSA

CLKA1

CLKA2

REFSEL

DCXO

REF1

CLKA[1:4]

CLKB[1:4]

Failsafe^TM

REF2

FBK

PLL

Block

VDDB

VDDA

VSSB

CLKB3

CLKB4

VDDB

VDDC

XIN

VSSA

CLKA3

CLKA4

VDDA

FAIL#/SAFE

XOUT

Decoder

FAIL# /SAFE

S[4:1]

28 pin SSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07518 Rev. *A

Revised May 12, 2004

12 3 4 5 6 7...12

中文翻译

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与CY23FS08相关器件

型号	品牌	获取价格	描述	数据表
CY23FS08_06	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS08_11	CYPRESS	获取价格	Failsafe? 2.5 V/3.3 V Zero Delay Buffer
CY23FS08_12	CYPRESS	获取价格	Failsafeâ¢ 2.5 V/3.3 V Zero Delay Buffer
CY23FS08-04	CYPRESS	获取价格	FailSafe⑩ 1.8V Zero Delay Buffer
CY23FS08OC	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS08OCT	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS08OI	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS08OIT	CYPRESS	获取价格	Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS08OXC	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
CY23FS08OXCT	CYPRESS	获取价格	Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer

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