Datasheet > CY23S02_12

CY23S02_12

更新时间： 2024-11-06 12:50:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		倍频器
页数	文件大小	规格书
10页	268K
描述
Spread Awareâ¢, Frequency Multiplier, and Zero Delay Buffer

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数据手册

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CY23S02_12 数据手册

CY23S02

Spread Aware™, Frequency Multiplier,

and Zero Delay Buffer

Features

■ Spread Aware™ — designed to work with SSFTG reference

Table 1. Configuration Options

signals

FBIN

OUT1

OUT2

FS0

FS1

OUT1

2 X REF

4 X REF

REF

OUT2

REF

■ 90 ps typical jitter OUT2

■ 200 ps typical jitter OUT1

2 X REF

REF/2

■ 65 ps typical output-to-output skew

■ 90 ps typical propagation delay

■ Voltage range: 3.3 V ± 5%, or 5 V ± 10%

■ Output frequency range: 20 MHz - 133 MHz

■ Two outputs

8 X REF

4 X REF

8 X REF

2 X REF

16 X REF

4 X REF

2 X REF

4 X REF

REF

8 X REF

■ Configuration options allow various multiplication of the

reference frequency, refer to Table 1 to determine the

specific option which meets your multiplication needs

■ Available in 8-pin SOIC package

Block Diagram

Pin Configuration

External feedback connection to

OUT1 or OUT2, not both

FBIN

OUT2

VDD

OUT1

FS1

GND

FS0

÷Q

FS1

Phase

Detector

Charge

Pump

Reference

Input

Loop

Filter

Output

Buffer

OUT1

OUT2

VCO

Output

Buffer

÷2

Cypress Semiconductor Corporation

Document #: 38-07155 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 8, 2011

12 3 4 5 6 7...10

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