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CY23S02_05 PDF预览

CY23S02_05

更新时间: 2024-11-06 04:37:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 倍频器
页数 文件大小 规格书
7页 163K
描述
Spread Aware⑩, Frequency Multiplier and Zero Delay Buffer

CY23S02_05 数据手册

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CY23S02  
Spread Aware™, Frequency Multiplier and  
Zero Delay Buffer  
Table 1. Configuration Options  
Features  
FBIN  
OUT1  
OUT1  
OUT1  
OUT1  
OUT2  
OUT2  
OUT2  
OUT2  
FS0  
0
1
0
1
0
1
0
1
FS1  
0
0
1
1
0
0
1
1
OUT1  
2 X REF  
4 X REF  
REF  
8 X REF  
4 X REF  
8 X REF  
2 X REF  
16 X REF  
OUT2  
REF  
2 X REF  
REF/2  
4 X REF  
2 X REF  
4 X REF  
REF  
• Spread Aware™—designed to work with SSFTG  
reference signals  
• 90ps typical jitter OUT2  
• 200ps typical jitter OUT1  
• 65ps typical output-to-output skew  
• 90ps typical propagation delay  
• Voltage range: 3.3V±5%, or 5V±10%  
• Output frequency range: 20MHz-133MHz  
• Two outputs  
• Configuration options allow various multiplication of  
the reference frequency, refer to Table 1 to determine  
the specific option which meets your multiplication  
needs  
8 X REF  
• Available in 8-pin SOIC package  
Block Diagram  
Pin Configuration  
External feedback connection to  
FBIN  
OUT1 or OUT2, not both  
FBIN  
IN  
GND  
FS0  
1
2
3
4
8
7
6
5
OUT2  
VDD  
OUT1  
FS1  
FS0  
FS1  
÷Q  
Phase  
Charge  
Pump  
IN  
Detector  
Reference  
Input  
Loop  
Filter  
Output  
Buffer  
OUT1  
OUT2  
VCO  
Output  
Buffer  
÷2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07155 Rev. *C  
Revised June 7, 2005  

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