Datasheet > CY23FP12_12

CY23FP12_12

更新时间： 2024-11-18 11:51:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	612K
描述
200 MHz Field Programmable Zero Delay Buffer

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数据手册

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CY23FP12_12 数据手册

CY23EP05

2.5 V or 3.3 V,10-220-MHz, Low Jitter,

5 Output Zero Delay Buffer

Features

Functional Description

■ 10 MHz to 220 MHz maximum operating range

The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to

distribute low-jitter high-speed clocks and is available in a 8-pin

■ Zero input-output propagation delay, adjustable by loading on

CLKOUT pin

SOIC package. It accepts one reference input, and drives out five

low-skew clocks. The –1H version operates up to 220 (200) MHz

frequencies at 3.3 V (2.5 V), and has a higher drive strength than

the –1 devices. All parts have on-chip PLLs which lock to an input

clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad.

■ Multiple low-skew outputs

❐ 30 ps typical output-output skew

❐ One input drives five outputs

■ 22 ps typical cycle-to-cycle jitter

■ 13 ps typical period jitter

The CY23EP05 PLL enters a power-down mode when there are

no rising edges on the REF input (< ~2 MHz). In this state, the

outputs are three-stated and the PLL is turned off, resulting in

less than 25 μA of current draw.

■ Standard and high drive strength options

■ Available in space-saving 150-mil SOIC package

■ 3.3 V or 2.5 V operation

The CY23EP05 is available in different configurations, as shown

in the Ordering Information table. The CY23EP05-1 is the base

part. The CY23EP05-1H is the high-drive version of the –1, and

its rise and fall times are much faster than the –1.

■ Industrial temperature available

These parts are not intended for 5 V input-tolerant applications.

Logic Block Diagram

CLKOUT

CLK1

PLL

REF

CLK2

CLK3

CLK4

Cypress Semiconductor Corporation

Document #: 38-07759 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 7, 2011

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