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CY23FP12OXIT PDF预览

CY23FP12OXIT

更新时间: 2024-11-05 22:08:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 203K
描述
200-MHz Field Programmable Zero Delay Buffer

CY23FP12OXIT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:5.68Is Samacsys:N
系列:23FP输入调节:MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.02 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:28实输出次数:12
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5,3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.3 mm最小 fmax:166.7 MHz
Base Number Matches:1

CY23FP12OXIT 数据手册

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CY23FP12  
200-MHz Field Programmable Zero Delay Buffer  
Features  
Functional Description  
• Fully field-programmable  
— Input and output dividers  
— Inverting/noninverting outputs  
The CY23FP12 is a high-performance fully field-program-  
mable 200 MHz zero delay buffer designed for high speed  
clock distribution. The integrated PLL is designed for low jitter  
and optimized for noise rejection. These parameters are  
critical for reference clock distribution in systems using  
high-performance ASICs and microprocessors.  
— Phase-locked loop (PLL) or fanout buffer configu-  
ration  
The CY23FP12 is fully programmable via volume or prototype  
programmers enabling the user to define an appli-  
cation-specific Zero Delay Buffer with customized input and  
output dividers, feedback topology (internal/external), output  
inversions, and output drive strengths. For additional flexibility,  
the user can mix and match multiple functions, listed in  
Table 2, and assign a particular function set to any one of the  
four possible S1-S2 control bit combinations. This feature  
allows for the implementation of four distinct personalities,  
selectable with S1-S2 bits, on a single programmed silicon.  
The CY23FP12 also features a proprietary auto-power-down  
circuit that shuts down the device in case of a REF failure,  
resulting in less than 50 µA of current draw.  
• 10-MHz to 200-MHz operating range  
• Split 2.5V or 3.3V outputs  
• Two LVCMOS reference inputs  
• Twelve low-skew outputs  
35ps typ. output-to-output skew (same freq)  
• 110 ps typ. cycle-cycle jitter (same freq)  
• Three-stateable outputs  
• < 50-µA shutdown current  
• Spread Aware  
• 28-pin SSOP  
The CY23FP12 provides twelve outputs grouped in two banks  
with separate power supply pins which can be connected  
independently to either a 2.5V or a 3.3V rail.  
• 3.3V operation  
• Industrial temperature available  
Selectable reference input is a fault tolerance feature which  
allows for glitch-free switch over to secondary clock source  
when REFSEL is asserted/deasserted.  
Pin Configuration  
Block Diagram  
SSOP  
VDDA  
VDDC  
Top View  
CLKA0  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
Lock Detect  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
REF2  
REF1  
REFSEL  
2
FBK  
CLKA0  
CLKA1  
3
CLKB0  
4
CLKB1  
5
VSSA  
VSSB  
CLKB2  
REFSEL  
REF1  
6
CLKA2  
CLKA3  
VDDA  
CLKA5  
VSSA  
VDDB  
7
÷M  
÷N  
100 to  
400MHz  
PLL  
CLKB3  
÷1  
÷2  
÷3  
÷4  
÷X  
REF2  
8
VDDB  
FBK  
9
VSSA  
VSSB  
10  
11  
12  
13  
14  
CLKB4  
CLKB5  
19  
18  
CLKA4  
CLKA5  
VDDA  
VSSC  
S1  
CLKB0  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
VDDB  
VDDC  
S2  
17  
16  
15  
Test Logic  
Function  
Selection  
S[2:1]  
VSSC  
CLKB5  
VSSB  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07246 Rev. *E  
Revised December 13, 2004  

CY23FP12OXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY23FP12OXI CYPRESS

完全替代

200-MHz Field Programmable Zero Delay Buffer
CY23FP12OXCT CYPRESS

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200-MHz Field Programmable Zero Delay Buffer
CY23FP12OXC CYPRESS

类似代替

200-MHz Field Programmable Zero Delay Buffer

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