CY23FP12
200-MHz Field Programmable Zero Delay Buffer
Features
Functional Description
• Fully field-programmable
— Input and output dividers
— Inverting/noninverting outputs
The CY23FP12 is a high-performance fully field-program-
mable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using
high-performance ASICs and microprocessors.
— Phase-locked loop (PLL) or fanout buffer configu-
ration
The CY23FP12 is fully programmable via volume or prototype
programmers enabling the user to define an appli-
cation-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12 also features a proprietary auto-power-down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50 µA of current draw.
• 10-MHz to 200-MHz operating range
• Split 2.5V or 3.3V outputs
• Two LVCMOS reference inputs
• Twelve low-skew outputs
— 35ps typ. output-to-output skew (same freq)
• 110 ps typ. cycle-cycle jitter (same freq)
• Three-stateable outputs
• < 50-µA shutdown current
• Spread Aware
• 28-pin SSOP
The CY23FP12 provides twelve outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5V or a 3.3V rail.
• 3.3V operation
• Industrial temperature available
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/deasserted.
Pin Configuration
Block Diagram
SSOP
VDDA
VDDC
Top View
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
Lock Detect
1
28
27
26
25
24
23
22
21
20
REF2
REF1
REFSEL
2
FBK
CLKA0
CLKA1
3
CLKB0
4
CLKB1
5
VSSA
VSSB
CLKB2
REFSEL
REF1
6
CLKA2
CLKA3
VDDA
CLKA5
VSSA
VDDB
7
÷M
÷N
100 to
400MHz
PLL
CLKB3
÷1
÷2
÷3
÷4
÷X
REF2
8
VDDB
FBK
9
VSSA
VSSB
10
11
12
13
14
CLKB4
CLKB5
19
18
CLKA4
CLKA5
VDDA
VSSC
S1
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
VDDB
VDDC
S2
17
16
15
Test Logic
Function
Selection
VSSC
CLKB5
VSSB
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07246 Rev. *E
Revised December 13, 2004