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CY23FP12OXC-002 PDF预览

CY23FP12OXC-002

更新时间: 2024-11-18 09:41:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 512K
描述
200-MHz Field Programmable Zero Delay Buffer

CY23FP12OXC-002 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:5.30 MM, LEAD FREE, SSOP-28
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.7系列:23FP
输入调节:MUXJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:10.2 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.12 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:28
实输出次数:12最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH电源:2.5,3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
最小 fmax:200 MHzBase Number Matches:1

CY23FP12OXC-002 数据手册

 浏览型号CY23FP12OXC-002的Datasheet PDF文件第2页浏览型号CY23FP12OXC-002的Datasheet PDF文件第3页浏览型号CY23FP12OXC-002的Datasheet PDF文件第4页浏览型号CY23FP12OXC-002的Datasheet PDF文件第5页浏览型号CY23FP12OXC-002的Datasheet PDF文件第6页浏览型号CY23FP12OXC-002的Datasheet PDF文件第7页 
CY23FP12-002  
200-MHz Field Programmable Zero  
Delay Buffer  
Features  
Functional Description  
Pre-programmed configuration  
The CY23FP12-002 is a pre-programmed version of the  
CY23FP12. It features a high-performance fully field-program-  
mable 200-MHz zero delay buffer designed for high-speed clock  
distribution. The integrated PLL is designed for low jitter and  
optimized for noise rejection. These parameters are critical for  
reference clock distribution in systems using high-performance  
ASICs and microprocessors.  
Fully field-programmable  
Input and output dividers  
Inverting/noninverting outputs  
Phase-locked loop (PLL) or fanout buffer configuration  
10 MHz to 200 MHz operating range  
Split 2.5-V or 3.3-V outputs  
The CY23FP12-002 is fully programmable through volume or  
prototype programmers, enabling the user to define an  
application-specific zero delay buffer with customized input and  
output dividers, feedback topology (internal/external), output  
inversions, and output drive strengths. For additional flexibility,  
the user can mix and match multiple functions, listed in Table 2  
on page 5, and assign a particular function set to any one of the  
four possible S1-S2 control bit combinations. This feature  
enables the implementation of four distinct personalities,  
selectable with S1-S2 bits, on a single programmed silicon. The  
CY23FP12-002 also features a proprietary auto power down  
circuit that shuts down the device in case of a REF failure,  
resulting in less than 50 μA of current draw.  
Two low-voltage complementary metal oxide semiconductor  
(LVCMOS) reference inputs  
Twelve low-skew outputs  
Output-output skew < 200 ps  
Device-device skew < 500 ps  
Input-output skew < 250 ps  
Cycle-cycle jitter < 100 ps (typical)  
Three-stateable outputs  
The CY23FP12-002 provides 12 outputs grouped in two banks  
with separate power supply pins which can be connected  
independently to either a 2.5 V or a 3.3 V rail.  
Less than 50 μA shutdown current  
Spread Aware™  
28-pin shrunk small outline package (SSOP)  
3.3-V operation  
Selectable reference input is a fault tolerance feature which  
allows for glitch-free switch over to secondary clock source when  
REFSEL is asserted/deasserted.  
Logic Block Diagram  
VDDA  
VDDC  
CLKA0  
Lock Detect  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
CLKA5  
REFSEL  
REF1  
÷M  
100 to  
400MHz  
PLL  
÷1  
REF2  
VSSA  
FBK  
÷N  
÷2  
VDDB  
÷3  
÷4  
CLKB0  
÷X  
CLKB1  
÷2X  
CLKB2  
CLKB3  
Test Logic  
CLKB4  
Function  
Selection  
S[2:1]  
CLKB5  
VSSB  
VSSC  
Cypress Semiconductor Corporation  
Document #: 38-07644 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 18, 2011  
[+] Feedback  

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