Datasheet > CY23FP12-002

CY23FP12-002

更新时间： 2024-11-06 02:59:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	212K
描述
200-MHz Field Programmable Zero Delay Buffer

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CY23FP12-002 数据手册

CY23FP12-002

200-MHz Field Programmable Zero Delay Buffer

Features

Functional Description

• Pre-programmed Configurations

• Fully field-programmable

— Input and output dividers

— Inverting/noninverting outputs

The CY23FP12-002 is a pre-programmed version of the

CY23FP12. It features a high-performance fully field-program-

mable 200 MHz zero delay buffer designed for high speed

clock distribution. The integrated PLL is designed for low jitter

and optimized for noise rejection. These parameters are

critical for reference clock distribution in systems using high-

performance ASICs and microprocessors.

— Phase-locked loop (PLL) or fanout buffer configu-

ration

The CY23FP12-002 is fully programmable via volume or

prototype programmers enabling the user to define an appli-

cation-specific Zero Delay Buffer with customized input and

output dividers, feedback topology (internal/external), output

inversions, and output drive strengths. For additional flexibility,

the user can mix and match multiple functions, listed in

Table 2, and assign a particular function set to any one of the

four possible S1-S2 control bit combinations. This feature

allows for the implementation of four distinct personalities,

selectable with S1-S2 bits, on a single programmed silicon.

The CY23FP12-002 also features a proprietary auto-power-

down circuit that shuts down the device in case of a REF

failure, resulting in less than 50 µA of current draw.

The CY23FP12-002 provides twelve outputs grouped in two

banks with separate power supply pins which can be

connected independently to either a 2.5V or a 3.3V rail.

Selectable reference input is a fault tolerance feature which

allows for glitch-free switch over to secondary clock source

when REFSEL is asserted/de-asserted.

• 10-MHz to 200-MHz operating range

• Split 2.5V or 3.3V outputs

• Two LVCMOS reference inputs

• Twelve low-skew outputs

— Output-output skew < 200 ps

— Device-device skew < 500 ps

• Input-output skew < 250 ps

• Cycle-cycle jitter < 100 ps (typical)

• Three-stateable outputs

• < 50-µA shutdown current

• Spread Aware

• 28-pin SSOP

• 3.3V operation

• Industrial temperature available

Block Diagram

Pin Configuration

SSOP

VDDA

VDDC

Top View

CLKA0

REF2

REF1

REFSEL

Lock Detect

CLKA1

CLKA2

CLKA3

CLKA4

FBK

CLKA0

CLKA1

CLKB0

CLKB1

V_SSA

V_SSB

CLKB2

REFSEL

REF1

CLKA2

CLKA3

V_DDA

CLKB3

CLKA5

VSSA

VDDB

÷M

÷N

100 to

400MHz

PLL

÷1

÷2

÷3

÷4

V_DDB

REF2

V_SSA

V_SSB

FBK

CLKB4

CLKB5

CLKA4

CLKA5

V_DDA

V_SSC

CLKB0

CLKB1

CLKB2

CLKB3

CLKB4

V_DDB

V_DDC

÷X

÷2X

Test Logic

Function

Selection

S[2:1]

VSSC

CLKB5

VSSB

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07644 Rev. **

Revised February 25, 2004

12 3 4 5 6 7...10

中文翻译

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与CY23FP12-002相关器件

型号	品牌	获取价格	描述	数据表
CY23FP12-002_11	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OC	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OC-002	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OC-002T	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OCT	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OI	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OI-002	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OI-002T	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OIT	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY23FP12OXC	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer

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