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CY23EP09ZXI-1H PDF预览

CY23EP09ZXI-1H

更新时间： 2024-11-21 03:07:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 355K
描述
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer

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中文翻译

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CY23EP09ZXI-1H 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：0.93
其他特性：ALSO OPERATES AT 3.3V SUPPLY系列：23EP
输入调节：STANDARDJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：16
实输出次数：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/3.3 VProp。Delay @ Nom-Sup：2.1 ns
传播延迟（tpd）：4.4 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.11 ns座面最大高度：1.1 mm
子类别：Clock Drivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
最小 fmax：10 MHzBase Number Matches：1

CY23EP09ZXI-1H 数据手册

 浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第2页浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第3页浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第4页浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第5页浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第6页浏览型号CY23EP09ZXI-1H的Datasheet PDF文件第7页 
CY23EP09  
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output  
Zero Delay Buffer  
Features  
Functional Description  
• 10 MHz to 220 MHz maximum operating range  
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed  
to distribute high-speed clocks and is available in a 16-pin  
SOIC or TSSOP package. The -1H version operates up to 220  
(200) MHz frequencies at 3.3V (2.5V), and has higher drive  
than the -1 devices. All parts have on-chip PLLs that lock to an  
input clock on the REF pin. The PLL feedback is on-chip and  
is obtained from the CLKOUT pad.  
• Zero input-output propagation delay, adjustable by  
loading on CLKOUT pin  
• Multiple low-skew outputs  
— 45 ps typical output-output skew  
— One input drives nine outputs, grouped as 4 + 4 + 1  
• 25 ps typical cycle-to-cycle jitter  
• 15 ps typical period jitter  
There are two banks of four outputs each, which can be  
controlled by the Select inputs as shown in the “Select Input  
Decoding” table on page 2. If all output clocks are not required,  
BankB can be three-stated. The select inputs also allow the  
input clock to be directly applied to the outputs for chip and  
system testing purposes.  
• Standard and High drive strength options  
• Available in space-saving 16-pin 150-mil SOIC or  
4.4-mm TSSOP packages  
The PLL enters a power-down mode when there are no rising  
edges on the REF input (less than ~2 MHz). In this state, the  
outputs are three-stated and the PLL is turned off, resulting in  
less than 25 µA of current draw.  
• 3.3V or 2.5V operation  
• Industrial temperature available  
In the special case when S2:S1 is 1:0, the PLL is bypassed  
and REF is output from DC to the maximum allowable  
frequency. The part behaves like a non-zero delay buffer in this  
mode, and the outputs are not tri-stated.  
The CY23EP09 is available in different configurations, as  
shown in the Ordering Information table. The CY23EP09-1 is  
the base part. The CY23EP09-1H is the high-drive version of  
the -1, and its rise and fall times are much faster than the -1.  
These parts are not intended for 5V input-tolerant applications  
Pin Configuration  
Block Diagram  
CLKOUT  
PLL  
MUX  
Top View  
REF  
CLKA1  
CLKA2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
REF  
CLKOUT  
CLKA1  
CLKA4  
CLKA3  
VDD  
CLKA2  
VDD  
CLKA3  
CLKA4  
GND  
GND  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
CLKB2  
S2  
S2  
Select Input  
Decoding  
S1  
Cypress Semiconductor Corporation  
Document #: 38-07760 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 5, 2005  
1234567...13

中文翻译

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CY23EP09ZXI-1H 替代型号

型号 品牌 替代类型 描述 数据表
CY23EP09SXI-1T CYPRESS

完全替代

 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1H CYPRESS

完全替代

 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
CY23EP09SXI-1 CYPRESS

完全替代

 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer

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