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CY2215PVC-1T

更新时间： 2024-11-09 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 107K
描述
Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO48, SSOP-48

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中文翻译

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CY2215PVC-1T 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.83
Is Samacsys：N其他特性：ALSO REQUIRES 3.3V SUPPLY
JESD-30 代码：R-PDSO-G48长度：15.875 mm
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：133.33 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率：14.318 MHz认证状态：Not Qualified
座面最大高度：2.794 mm最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CY2215PVC-1T 数据手册

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215  
CY2215  
133-MHz Spread Spectrum Frequency Timing Generator  
Features  
Benefits  
• Mixed 2.5V and 3.3V Operation  
Usable with Pentium II, K6, and 6x86 Processors  
• Multiple output clocks at different frequencies  
— Three CPU clocks, up to 133 MHz  
— Ten synchronous PCI clocks, 1 free-running  
— One CPU/2 clock, at one-half the CPU frequency  
— Three 66 MHz clocks  
Single-chip main motherboard clock generator  
— Driven together, support 3 CPUs and a chipset  
— Support for 4 PCI slots and chipset  
— Drives up to two main memory clock generators,  
including DRCG  
— Support for multiple AGP slots  
— One synchronous IOAPIC clock, at 16.67 MHz  
— One 48 MHz clock  
— Two reference clocks at 14.318 MHz  
— Support multiprocessing systems  
— Supports USB frequencies and I/O chip  
— Supports ISA slots and I/O chip  
• Spread Spectrum clocking  
Enables reduction of EMI in some systems  
— 32.5 kHz modulation frequency at 133 MHz  
— 33.1 kHZ modulation frequency at 100 MHz  
— EPROM programmable percentage of spreading.  
Default is –0.5%, which is recommended by Intel®.  
• Power-down features  
Supports mobile systems  
• Three Select inputs  
Supports up to eight CPU clock frequencies  
Meet tight system timing requirements at high frequency  
Enables ATE and “bed of nails” testing  
• Low-skew and low-jitter outputs  
• OE and Test Mode support  
• 48-pin SSOP package  
Widely available, standard package enables lower cost  
SSOP  
Top View  
Logic Block Diagram  
SEL0  
V
V
SSREF  
1
2
3
4
48  
SEL0/REFCLK0  
REFCLK1  
REFCLK0 (14.318 MHz)  
REFCLK1 (14.318 MHz)  
47  
46  
DDAPIC  
IOAPIC  
V
DDREF  
XTALIN  
45  
44  
43  
42  
V
V
SSAPIC  
XTALOUT  
5
DDCPU/2  
CPUCLK [0-2]  
V
SSPCI  
CPUCLK/2  
6
PCICLK_F  
V
V
SSCPU/2  
DDCPU  
7
XTALIN  
PCICLK1  
41  
8
14.318  
CPUCLK/2  
Divider,  
EPROM-Prog  
Delay  
and  
Stop Logic  
MHz  
OSC.  
CPU  
PLL  
V
40  
39  
38  
DDPCI  
9
CPUCLK2  
V
XTALOUT  
SEL1  
PCICLK2  
SSCPU  
10  
11  
PCICLK_F (33.33 MHz)  
PCICLK3  
PCICLK4  
V
DDCPU  
CPUCLK1  
CPUCLK0  
37  
36  
35  
34  
33  
12  
13  
PCICLK5  
PCICLK [1-9] (33.33 MHz)  
IOAPIC (16.67 MHz)  
EPROM  
SEL133  
V
14  
15  
16  
V
SSPCI  
SSCPU  
SPREAD  
AV  
DD  
PCICLK6  
PCICLK7  
AV  
SS  
17  
18  
19  
20  
21  
22  
23  
24  
PWR_DWN  
SPREAD  
32  
31  
30  
V
DDPCI  
66CLK [0-2] (66.67 MHz)  
PCICLK8  
PCICLK9  
PWR_DWN  
SEL1  
NC  
V
SS66  
29  
28  
27  
26  
SYS  
PLL  
48 MHz CLK  
66CLK0  
V
DD48  
66CLK1  
66CLK2  
48CLK  
V
SS48  
V
SEL133  
25  
DD66  
Intel and Pentium are registered trademarks of Intel Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 15, 2000, rev. *A  
12345678

中文翻译

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