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CY2220PVC-2T PDF预览

CY2220PVC-2T

更新时间: 2024-11-29 21:02:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
11页 126K
描述
Processor Specific Clock Generator, 133MHz, CMOS, PDSO56, SSOP-56

CY2220PVC-2T 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
JESD-30 代码:R-PDSO-G56长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY2220PVC-2T 数据手册

 浏览型号CY2220PVC-2T的Datasheet PDF文件第2页浏览型号CY2220PVC-2T的Datasheet PDF文件第3页浏览型号CY2220PVC-2T的Datasheet PDF文件第4页浏览型号CY2220PVC-2T的Datasheet PDF文件第5页浏览型号CY2220PVC-2T的Datasheet PDF文件第6页浏览型号CY2220PVC-2T的Datasheet PDF文件第7页 
0
CY2220  
133-MHz Spread Spectrum Clock Synthesizer/Driver  
with Differential CPU Outputs  
Features  
Benefits  
• Compliant to Intel® CK00 Clock Synthesizer/Driver  
Supports next generation Pentium® processors using differen-  
Specifications  
tial clock drivers  
Multiple output clocks at different frequencies  
Four pairs of differential CPU outputs, up to 133 MHz  
Ten synchronous PCI clocks  
Motherboard clock generator  
Support Multiple CPUs and a chipset  
Support for PCI slots and chipset  
Two Memory Reference clocks, 180 degrees out of  
Drives up to two Direct RambusClock Generators  
phase  
(DRCG)  
Four AGP and Hub Link clocks at 66 MHz  
Two 48-MHz clocks  
Supports USB host controller and SuperI/O chip  
Supports ISA slots and I/O chip  
Two reference clocks at 14.318 MHz  
Spread Spectrum clocking  
Enables reduction of EMI and overall system cost  
31 kHz modulation frequency  
Default is 0.6%, which is recommended by Intel  
Power-down features  
Enables ACPI compliant designs  
Three Select inputs  
Supports up to eight CPU clock frequencies  
Meets tight system timing requirements at high frequency  
Enables ATE and bed of nailstesting  
Low-skew and low-jitter outputs  
OE and Test Mode support  
56-pin SSOP package  
Widely available, standard package enables lower cost  
Pin Configuration  
Logic Block Diagram  
SSOP  
Top View  
VDDMEM  
1
2
3
4
5
6
56  
55  
54  
VSSREF  
REFCLK [01]  
CPUCLK [03]  
MemRef  
MemRefB  
VSSMEM  
REFCLK0/MultSel_0  
REFCLK1/MultSel_1  
VDDREF  
53  
52  
51  
50  
MultSel0  
MultSel1  
SPREAD  
XTALIN  
XTALOUT  
VSSPCI  
CPUCLK_3  
CPUCLK_3B  
VDDCPU  
7
PCICLK_0  
49  
48  
47  
46  
45  
44  
43  
42  
41  
8
CPUCLKB [03]  
XTALIN  
14.318  
MHz  
OSC.  
Divider  
and  
Stop Logic  
CPU  
PLL  
PCICLK_1  
VDDPCI  
9
CPUCLK_2  
CPUCLK_2B  
10  
11  
XTALOUT  
MemRef, MemRefB  
VSSCPU  
PCICLK_2  
PCICLK_3  
VSSPCI  
CPUCLK_1  
CPUCLK_1B  
VDDCPU  
12  
13  
SELA  
SELB  
SEL133  
PCICLK [09] (33.33 MHz)  
EPROM  
14  
15  
16  
17  
18  
PCICLK_4  
PCICLK_5  
VDDPCI  
CPUCLK_0  
CPUCLK_0B  
VSSCPU  
SPREAD  
PWR_DWN  
40  
39  
38  
37  
36  
35  
34  
PCICLK_6  
PCICLK_7  
VSSPCI  
3V66 [03] (66.67 MHz)  
IREF  
19  
20  
AVDD  
AVSS  
PCICLK_8  
SYS  
PLL  
USBCLK [0-1] (48 MHz)  
PCICLK_9  
VDDPCI  
VDD3V66  
21  
22  
23  
24  
25  
3V66_3  
3V66_2  
VSS3V66  
Sel133  
VSSUSB  
33  
32  
31  
30  
29  
USBCLK0/SelA  
VSS3V66  
3V66_1  
USBCLK1/SelB  
VDDUSB  
26  
27  
28  
3V66_0  
VDD3V66  
PWR_DWN  
Intel and Pentium are registered trademarks of Intel Corporation.  
Direct Rambus is a trademark of Rambus, Inc.  
Cypress Semiconductor Corporation  
Document #: 38-07206 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised November 15, 2001  

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