CY22313

更新时间： 2024-11-29 09:41:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
9页	159K
描述
Two-PLL Clock Generator with Direct Rambus-TM (Lite) Support

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中文翻译

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数据手册

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CY22313 数据手册

CY22313

Two-PLL Clock Generator with

Direct Rambus™ (Lite) Support

Benefits

Features

• Two integrated phase-locked loops (PLLs)

• Ultra-accurate PLLs

• High-performance PLL tailored for multimedia applica-

tions

• Frequency tolerance within 1 PPM on all frequencies

• Direct Rambus™ clock support

• Two input selects

• One pair of differential output drivers, identical speci-

fication to CY2212

• 3.45V core; 3.45V, 2.5V, 1.8V, and 1.675V outputs

• 24-pin TSSOP package

• Selectable 54.0-/53.946-MHz output and

294.912-/393.216-MHz Rambus^®output

• Supports output voltage requirements

• Industry-standard packaging saves on board space

Block Diagram

XIN

XTAL.

OSC.

XOUT

Divide by 2

Divider

LCLK

CONFIGURATION

LOGIC

54MOUT

PLL1

PLL2

CLK

CLKB

Pin Configuration

Frequency Select Tables

54MOUT

53.94605395

Unit

MHz

PPM

–1

VDDRP

VSSRP

Xout

VDDR

VSSR

CLK

Xin

CLK, CLKB

294.912

393.216

Unit

MHz

PPM

CLKB

VSSR

VDDR

VSSVPA

VDDVPA

VSS54

54MOUT

LCLK

9.216

Unit

MHz

PPM

VDDL

VSSL

LCLK

VSSVP

VDD54

VDDVP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07434 Rev. *E

Revised June 29, 2004

12 3 4 5 6 7...9

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