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CY22381_08

更新时间: 2024-11-29 06:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器闪存
页数 文件大小 规格书
9页 346K
描述
Three-PLL General Purpose FLASH Programmable Clock Generator

CY22381_08 数据手册

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CY22381  
Three-PLL General Purpose FLASH  
Programmable Clock Generator  
Improves frequency accuracy over temperature, age, process,  
and initial offset  
Features  
Three integrated phase-locked loops  
Non-volatile programming enables easy customization,  
ultra-fast turnaround, performance tweaking, design timing  
margin testing, inventory control, lower part count, and more  
secureproductsupply. Canalsobeprogrammedmultipletimes  
which reduces programming errors and provides an easy  
upgrade path for existing designs  
Ultra-wide divide counters (eight-bit Q, eleven-bit P, and  
seven-bit post divide)  
Improved linear crystal load capacitors  
Flash programmability  
In-house programming of samples and prototype quantities is  
available using the CY3672 FTG development Kit. Production  
quantities are available through Cypress’s value-added  
distribution partners or by using third party programmers from  
BP Microsystems, HiLo Systems, and others.  
Field programmability  
Low-jitter, high-accuracy outputs  
Power-management options (Shutdown, OE, Suspend)  
Configurable crystal drive strength  
Frequency select option through external LVTTL Input  
3.3V operation  
Performance suitable for high-end multimedia,  
communications, industrial, A/D converters, and consumer  
applications  
Supports numerous low-power application schemes and  
reduces EMI by allowing unused outputs to be turned off  
Eight-pin SOIC package  
CyClocks RT™ support  
Adjust crystal drive strength for compatibility with virtually all  
crystals  
Benefits  
External frequency select option for PLL1, CLKA, and CLKB  
Generates up to three unique frequencies on three outputs up  
to 200 MHz from an external source. Functional upgrade for  
current CY2081 family.  
Industry standard supply voltage  
Industry standard packaging saves on board space  
Easy-to-use software support for design entry  
Allows for 0 ppm frequency generation and frequency  
conversion under the most demanding applications  
Logic Block Diagram  
XTALIN  
OSC.  
XTALOUT  
PLL1  
Divider  
7-BIT  
CLKC  
11-BIT P  
8-BIT Q  
CONFIGURATION  
FLASH  
4 × 3  
Crosspoint  
Switch  
PLL2  
Divider  
7-BIT  
11-BIT P  
8-BIT Q  
CLKB  
CLKA  
SHUTDOWN/OE  
FS/SUSPEND  
PLL3  
Divider  
7-BIT  
11-BIT P  
8-BIT Q  
Cypress Semiconductor Corporation  
Document #: 38-07012 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 10, 2008  
[+] Feedback  

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