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CY2220PVC-2 PDF预览

CY2220PVC-2

更新时间： 2024-11-08 22:08:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动器时钟
页数 文件大小 规格书
11页 130K
描述
133-MHz Spread Spectrum Clock Synthesizer/Driver With Differential CPU Outputs

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中文翻译

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CY2220PVC-2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-56
针数：56Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.81JESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：18.415 mm
端子数量：56最高工作温度：70 °C
最低工作温度：最大输出时钟频率：133 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：2.794 mm
子类别：Clock Generators最大压摆率：250 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CY2220PVC-2 数据手册

 浏览型号CY2220PVC-2的Datasheet PDF文件第2页浏览型号CY2220PVC-2的Datasheet PDF文件第3页浏览型号CY2220PVC-2的Datasheet PDF文件第4页浏览型号CY2220PVC-2的Datasheet PDF文件第5页浏览型号CY2220PVC-2的Datasheet PDF文件第6页浏览型号CY2220PVC-2的Datasheet PDF文件第7页 
0
CY2220  
133-MHz Spread Spectrum Clock Synthesizer/Driver  
with Differential CPU Outputs  
Features  
Benefits  
• Compliant to Intel® CK00 Clock Synthesizer/Driver  
Supports next generation Pentium® processors using differen-  
Specifications  
tial clock drivers  
• Multiple output clocks at different frequencies  
—Four pairs of differential CPU outputs, up to 133 MHz  
—Ten synchronous PCI clocks  
Motherboard clock generator  
—Support Multiple CPUs and a chipset  
—Support for PCI slots and chipset  
—Two Memory Reference clocks, 180 degrees out of  
—Drives up to two Direct Rambus™ Clock Generators  
phase  
(DRCG)  
—Four AGP and Hub Link clocks at 66 MHz  
—Two 48-MHz clocks  
—Supports USB host controller and SuperI/O chip  
—Supports ISA slots and I/O chip  
—Two reference clocks at 14.318 MHz  
• Spread Spectrum clocking  
Enables reduction of EMI and overall system cost  
—31 kHz modulation frequency  
—Default is –0.6%, which is recommended by Intel  
• Power-down features  
Enables ACPI compliant designs  
• Three Select inputs  
Supports up to eight CPU clock frequencies  
Meets tight system timing requirements at high frequency  
Enables ATE and “bed of nails” testing  
• Low-skew and low-jitter outputs  
• OE and Test Mode support  
• 56-pin SSOP package  
Widely available, standard package enables lower cost  
Pin Configuration  
Logic Block Diagram  
SSOP  
Top View  
V
DDMEM  
1
2
3
4
5
6
56  
55  
54  
V
SSREF  
REFCLK [0–1]  
CPUCLK [0–3]  
MemRef  
REFCLK0/MultSel_0  
REFCLK1/MultSel_1  
MemRefB  
V
V
53  
52  
51  
50  
SSMEM  
DDREF  
MultSel0  
MultSel1  
SPREAD  
XTALIN  
XTALOUT  
V
CPUCLK_3  
CPUCLK_3B  
SSPCI  
7
V
PCICLK_0  
PCICLK_1  
49  
48  
47  
46  
45  
44  
43  
42  
41  
DDCPU  
8
CPUCLKB [0–3]  
XTALIN  
14.318  
MHz  
OSC.  
Divider  
and  
Stop Logic  
CPU  
PLL  
9
CPUCLK_2  
CPUCLK_2B  
V
DDPCI  
10  
11  
XTALOUT  
MemRef, MemRefB  
V
PCICLK_2  
PCICLK_3  
SSCPU  
CPUCLK_1  
12  
13  
SELA  
SELB  
SEL133  
V
CPUCLK_1B  
SSPCI  
PCICLK [0–9] (33.33 MHz)  
EPROM  
V
14  
15  
16  
17  
18  
PCICLK_4  
PCICLK_5  
DDCPU  
CPUCLK_0  
V
DDPCI  
CPUCLK_0B  
SPREAD  
PWR_DWN  
V
40  
39  
38  
37  
36  
35  
34  
PCICLK_6  
PCICLK_7  
SSCPU  
3V66 [0–3] (66.67 MHz)  
I
REF  
V
SSPCI  
19  
20  
AV  
AV  
DD  
SS  
PCICLK_8  
PCICLK_9  
SYS  
PLL  
USBCLK [0-1] (48 MHz)  
V
21  
22  
23  
24  
25  
DD3V66  
3V66_3  
3V66_2  
V
DDPCI  
Sel133  
V
V
33  
32  
31  
30  
29  
SSUSB  
SS3V66  
USBCLK0/SelA  
USBCLK1/SelB  
V
SS3V66  
3V66_1  
3V66_0  
26  
27  
28  
V
DDUSB  
PWR_DWN  
V
DD3V66  
Intel and Pentium are registered trademarks of Intel Corporation.  
Direct Rambus is a trademark of Rambus, Inc.  
Cypress Semiconductor Corporation  
Document #: 38-07206 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 30, 2002  
1234567...11

中文翻译

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