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CY22180SXC-XXX PDF预览

CY22180SXC-XXX

更新时间: 2024-11-09 04:37:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
8页 257K
描述
Very Low Jitter Field and Factory Programmable Clock Generator

CY22180SXC-XXX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.150 INCH, LEAD FREE, MS-012, SOIC-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.889 mm湿度敏感等级:3
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:133 MHz
认证状态:Not Qualified座面最大高度:1.727 mm
子类别:Clock Generators最大压摆率:15 mA
最大供电电压:3.45 V最小供电电压:3.13 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.8985 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY22180SXC-XXX 数据手册

 浏览型号CY22180SXC-XXX的Datasheet PDF文件第2页浏览型号CY22180SXC-XXX的Datasheet PDF文件第3页浏览型号CY22180SXC-XXX的Datasheet PDF文件第4页浏览型号CY22180SXC-XXX的Datasheet PDF文件第5页浏览型号CY22180SXC-XXX的Datasheet PDF文件第6页浏览型号CY22180SXC-XXX的Datasheet PDF文件第7页 
CY22180  
PRELIMINARY  
Very Low Jitter Field and Factory  
Programmable Clock Generator  
Benefits  
Features  
• Low period and cycle-to-cycle jitter  
— Typical pk-pk period jitter: 60 ps  
• InternalPLLgeneratesup to200 MHzoutput. Can generate  
custom frequencies from an external crystal or a driven  
source.  
• Wide output frequency range  
• In-house programming of samples and prototype quantities  
can be done using the CY3672-USB programmer and  
CY3619socketadapter. Productionquantitiesareavailable  
through Cypress’s value added distribution partners or by  
using third party programmers from BP Microsystems, HiLo  
Systems, and others.  
— Commercial temperature: 20–200 MHz  
— Industrial temperature: 20–166 MHz  
• Input frequency range  
— External crystal: 10–30 MHz fundamental crystal  
— External reference: 10–133 MHz clock  
• Integrated phase-locked loop (PLL)  
• Field programmable and factory programmed options  
• Programmable crystal load capacitor tuning array  
• 3.3V operation  
• Eliminates the need for expensive and difficult to use  
higher-order crystals.  
• Enables fine-tuning of output clock frequency by adjusting  
CLoad of the crystal. Eliminates the need for external CLoad  
capacitors.  
• Application compatibility in standard and low-power  
systems  
• Commercial and industrial temperature ranges  
• Power down or output enable function  
• Enables low-power state or output clocks to High-Z state.  
Logic Block Diagram  
Pin Configuration  
CY22180  
8-pin SOIC  
PLL  
6
1
OUTPUT  
DIVIDER  
XIN/CLKIN  
CXIN  
CLKOUT  
1
2
3
XIN/CLKIN  
VDD  
XOUT  
NC  
8
7
6
PROGRAMMABLE  
CONFIGURATION  
8
XOUT  
CXOUT  
5
PD#/OE  
CLKOUT  
REFOUT  
3
4
VSS  
REFOUT  
5
PD# or OE  
2
4
VDD  
VSS  
Cypress Semiconductor Corporation  
Document #: 001-15577 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 10, 2007  

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