CY22180

更新时间： 2024-11-29 04:37:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
8页	257K
描述
Very Low Jitter Field and Factory Programmable Clock Generator

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中文翻译

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数据手册

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CY22180 数据手册

CY22180

PRELIMINARY

Very Low Jitter Field and Factory

Programmable Clock Generator

Benefits

Features

• Low period and cycle-to-cycle jitter

— Typical pk-pk period jitter: 60 ps

• InternalPLLgeneratesup to200 MHzoutput. Can generate

custom frequencies from an external crystal or a driven

source.

• Wide output frequency range

• In-house programming of samples and prototype quantities

can be done using the CY3672-USB programmer and

CY3619socketadapter. Productionquantitiesareavailable

through Cypress’s value added distribution partners or by

using third party programmers from BP Microsystems, HiLo

Systems, and others.

— Commercial temperature: 20–200 MHz

— Industrial temperature: 20–166 MHz

• Input frequency range

— External crystal: 10–30 MHz fundamental crystal

— External reference: 10–133 MHz clock

• Integrated phase-locked loop (PLL)

• Field programmable and factory programmed options

• Programmable crystal load capacitor tuning array

• 3.3V operation

• Eliminates the need for expensive and difficult to use

higher-order crystals.

• Enables fine-tuning of output clock frequency by adjusting

C_Loadof the crystal. Eliminates the need for external C_Load

capacitors.

• Application compatibility in standard and low-power

systems

• Commercial and industrial temperature ranges

• Power down or output enable function

• Enables low-power state or output clocks to High-Z state.

Logic Block Diagram

Pin Configuration

CY22180

8-pin SOIC

PLL

OUTPUT

DIVIDER

XIN/CLKIN

CXIN

CLKOUT

XIN/CLKIN

VDD

XOUT

PROGRAMMABLE

CONFIGURATION

XOUT

C^XOUT

PD#/OE

CLKOUT

REFOUT

VSS

REFOUT

PD# or OE

VDD

VSS

Cypress Semiconductor Corporation

Document #: 001-15577 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 10, 2007

12 3 4 5 6 7 8

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