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CY14V104NA PDF预览

CY14V104NA

更新时间: 2024-11-05 09:41:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
22页 875K
描述
4-Mbit (512 K x 8 / 256 K x 16) nvSRAM 25 ns and 45 ns access times

CY14V104NA 数据手册

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CY14V104LA  
CY14V104NA  
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM  
4-Mbit (512  
K × 8 / 256 K × 16) nvSRAM  
Features  
Functional Description  
25 ns and 45 ns access times  
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,  
with a non-volatile element in each memory cell. The memory is  
Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16  
(CY14V104NA)  
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits  
each. The embedded non-volatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
non-volatile memory. The SRAM provides infinite read and write  
cycles, while independent non-volatile data resides in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
non-volatile elements (the STORE operation) takes place  
automatically at power-down. On power-up, data is restored to  
the SRAM (the RECALL operation) from the non-volatile  
memory. Both the STORE and RECALL operations are also  
available under software control.  
Hands off automatic STORE on power-down with only a small  
capacitor  
STORE to QuantumTrap non-volatile elements initiated by  
software, device pin, or AutoStore on power-down  
RECALL to SRAM initiated by software or power-up  
Infinite read, write, and recall cycles  
1-million STORE cycles to QuantumTrap  
20 year data retention  
Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V  
Industrial temperature  
48-ball fine-pitch ball grid array (FBGA) package  
Pb-free and restriction of hazardous substances (RoHS)  
compliance  
Logic Block Diagram [1, 2, 3]  
VCAP  
VCC  
V
CCQ  
Quatrum Trap  
2048 X 2048  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
POWER  
R
O
W
CONTROL  
STORE  
RECALL  
STORE/RECALL  
CONTROL  
D
E
C
O
D
E
R
HSB  
STATIC RAM  
ARRAY  
2048 X 2048  
A7  
A8  
A17  
SOFTWARE  
DETECT  
A14 - A2  
A18  
DQ0  
DQ1  
DQ2  
DQ3  
I
DQ4  
DQ5  
DQ6  
N
P
U
T
B
U
F
F
E
R
S
DQ7  
COLUMN I/O  
DQ8  
DQ9  
DQ10  
OE  
COLUMN DEC  
WE  
DQ11  
DQ12  
DQ13  
DQ14  
CE  
BLE  
A9 A10 A11 A12 A13 A14 A15 A16  
DQ15  
BHE  
Notes  
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.  
0
18  
0
17  
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.  
0
7
0
15  
3. BHE and BLE are applicable for × 16 configuration only.  
Cypress Semiconductor Corporation  
Document #: 001-53954 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 6, 2011  
[+] Feedback  

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