Datasheet > CY14V116G7

CY14V116G7

更新时间： 2024-11-06 01:07:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	1729K
描述
16-Mbit nvSRAM with Asynchronous NAND Interface

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CY14V116G7 数据手册

CY14V116F7

CY14V116G7

16-Mbit nvSRAM

with Asynchronous NAND Interface

16-Mbit nvSRAM with Asynchronous NAND Interface

Features

Functional Description

Cypress nvSRAM combines high-performance SRAM cells with

nonvolatile elements in a monolithic integrated circuit. The

■ 16-Mbit nonvolatile static random access memory (nvSRAM)

❐ Performance up to 33 MT/s per I/O

❐ Maximum data throughput using ×16 bus – 528 Mbps

❐ Industry-standard asynchronous NAND Flash interface with

reduced instruction set

❐ Shared address, data, and command bus

• Address and command bus is 8 bits

• Command is sent in one or two command cycles

• Address is sent in five address cycles

• Data bus width is ×8 or ×16 bits

embedded

nonvolatile

elements

incorporate

the

Silicon-Oxide-Nitride-Oxide-Silicon

(SONOS)

technology,

producing the world’s most reliable nonvolatile memory. The

SRAM can be read and written an infinite number of times. The

nonvolatile data resides in the nonvolatile elements and does not

change when data is written to the SRAM.

The CY14V116F7/CY14V116G7 nvSRAM provides access

through a standard asynchronous NAND interface and supports

the ×8 and ×16 interface options. In the case of ×16 interface,

data bytes are transmitted over the DQ[15:0] lines and has

double the throughput compared to the DQ[7:0] bus. The

CY14V116F7/ CY14V116G7 uses a highly multiplexed DQ bus

to transfer data, addresses, and instructions. All addresses and

commands are always transmitted over the data bus DQ[7:0].

Therefore, in the case of the ×16 bus interface, the upper eight

data bits DQ[15:8] become don’t care bits during the address and

command cycles. The CY14V116F7/CY14V116G7 uses five

control pins (CLE, ALE, CE, RE, and WE) to transfer command,

address, and data during read and write operations. Additional

I/O pins, such as write protect (WP), ready/busy (R/B), and HSB

STORE, are used to support features in the device.

■ Modes of operation:

❐ Asynchronous NAND Interface I/O with 30-ns access time

❐ Status Register with a software method for detecting the fol-

lowing:

• Nonvolatile STORE completion

• Pass/Fail condition of previous command

• Write protect status

■ Hands-off automatic STORE on power-down with only a small

capacitor

■ STORE to QuantumTrap nonvolatile elements is initiated by a

software command, a dedicated hardware pin, or AutoStore on

power-down

The asynchronous NAND interface nvSRAM is aligned to a

majority of the ONFI 1.0 specifications and supports data access

speed up to 33 MHz.

■ RECALL to SRAM initiated by software or power-up

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

For a complete list of related documentation, click here.

■ Data retention: 20 years at 85 C

■ Operating voltage

❐ Core V_CC= 2.7 V to 3.6 V; I/O V_CCQ= 1.70 V to 1.95 V

■ 165-ball fine-pitch ball grid array (FBGA) package

■ Industrial temperature: –40 C to +85 C

■ Restriction of hazardous substances (RoHS) compliant

Cypress Semiconductor Corporation

Document Number: 001-75528 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 5, 2018

12 3 4 5 6 7...32

中文翻译

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与CY14V116G7相关器件

型号	品牌	获取价格	描述	数据表
CY14V116G7-BZ30XI	CYPRESS	获取价格	16-Mbit nvSRAM with Asynchronous NAND Interface
CY14V116G7-BZ30XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V116G7-BZ30XIT	CYPRESS	获取价格	16-Mbit nvSRAM with Asynchronous NAND Interface
CY14V116G7-BZ30XIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V116N	CYPRESS	获取价格	16-Mbit (1024 K Ã 16) nvSRAM
CY14V116N-BZ30XI	CYPRESS	获取价格	16-Mbit (1024 K Ã 16) nvSRAM
CY14V116N-BZ30XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V116N-BZ30XIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14V116N-BZ45XI	CYPRESS	获取价格	16-Mbit (1024 K Ã 16) nvSRAM
CY14V256LA_13	CYPRESS	获取价格	256-Kbit (32 K x 8) nvSRAM

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