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CY14B256Q1_13 PDF预览

CY14B256Q1_13

更新时间: 2024-11-06 12:27:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
29页 1841K
描述
256-Kbit (32 K x 8) Serial (SPI) nvSRAM

CY14B256Q1_13 数据手册

 浏览型号CY14B256Q1_13的Datasheet PDF文件第2页浏览型号CY14B256Q1_13的Datasheet PDF文件第3页浏览型号CY14B256Q1_13的Datasheet PDF文件第4页浏览型号CY14B256Q1_13的Datasheet PDF文件第5页浏览型号CY14B256Q1_13的Datasheet PDF文件第6页浏览型号CY14B256Q1_13的Datasheet PDF文件第7页 
CY14B256Q1  
CY14B256Q2  
CY14B256Q3  
256-Kbit (32 K × 8) Serial (SPI) nvSRAM  
256-Kbit (32  
K × 8) Serial (SPI) nvSRAM  
Industry standard configurations  
Industrial temperature  
CY14B256Q1 has identical pin configuration to industry  
standard 8-pin NV memory  
Features  
256-Kbit nonvolatile static random access memory (nvSRAM)  
Internally organized as 32 K × 8  
8-pin dual flat no-lead (DFN) package and 16-pin small  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by user using  
HSB pin (Hardware STORE) or SPI instruction (Software  
STORE)  
outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
RECALL to SRAM initiated on power-up (Power-Up  
Functional Overview  
RECALL) or by SPI instruction (Software RECALL)  
The  
Cypress  
CY14B256Q1/CY14B256Q2/CY14B256Q3  
Automatic STORE on power-down with a small capacitor  
(except for CY14B256Q1)  
combines a 256-Kbit nvSRAM[1] with a nonvolatile element in  
each memory cell with serial SPI interface. The memory is  
organized as 32 K words of 8 bits each. The embedded  
nonvolatile elements incorporate the QuantumTrap technology,  
creating the world’s most reliable nonvolatile memory. The  
SRAM provides infinite read and write cycles, while the  
QuantumTrap cell provides highly reliable nonvolatile storage of  
data. Data transfers from SRAM to the nonvolatile elements  
(STORE operation) takes place automatically at power-down  
(except for CY14B256Q1). On power-up, data is restored to the  
SRAM from the nonvolatile memory (RECALL operation). The  
STORE and RECALL operations can also be initiated by the user  
through SPI instruction.  
High reliability  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
Data retention: 20 years  
High-speed serial peripheral interface (SPI)  
40-MHz clock rate  
Supports SPI mode 0 (0,0) and mode 3 (1,1)  
Write protection  
Hardware protection using Write Protect (WP) pin  
Software protection using Write Disable instruction  
Software block protection for 1/4,1/2, or entire array  
Configuration  
Low power consumption  
Single 3 V +20%, –10% operation  
Average active current of 10 mA at 40-MHz operation  
Feature  
CY14B256Q1 CY14B256Q2 CY14B256Q3  
AutoStore  
No  
Yes  
Yes  
Yes  
Yes  
Software  
STORE  
Yes  
Hardware  
STORE  
No  
No  
Yes  
Logic Block Diagram  
VCC  
VCAP  
QuantumTrap  
32 K X 8  
Power Control  
CS  
WP  
SCK  
Instruction decode  
Write protect  
Control logic  
STORE/RECALL  
Control  
STORE  
HSB  
SRAM Array  
HOLD  
RECALL  
32 K X 8  
Instruction  
register  
D0-D7  
A0-A14  
Address  
Decoder  
Data I/O register  
Status Register  
SO  
SI  
Note  
1. This device will be referred to as nvSRAM throughout the document.  
Cypress Semiconductor Corporation  
Document Number: 001-53882 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 27, 2013  

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