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CXK79M36C160GB-4 PDF预览

CXK79M36C160GB-4

更新时间: 2024-02-02 03:08:59
品牌 Logo 应用领域
索尼 - SONY 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 493K
描述
Standard SRAM, 512KX36, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209

CXK79M36C160GB-4 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA209,11X19,40针数:209
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:2.1 ns其他特性:PIPELINED ARCHITECTURE; LATE WRITE
最大时钟频率 (fCLK):250 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B209JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:STANDARD SRAM内存宽度:36
功能数量:1端子数量:209
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA209,11X19,40
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:1.5/1.8,1.8 V认证状态:Not Qualified
座面最大高度:2.3 mm最大待机电流:0.25 A
最小待机电流:1.7 V子类别:SRAMs
最大压摆率:0.55 mA最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:10
宽度:14 mm

CXK79M36C160GB-4 数据手册

 浏览型号CXK79M36C160GB-4的Datasheet PDF文件第2页浏览型号CXK79M36C160GB-4的Datasheet PDF文件第3页浏览型号CXK79M36C160GB-4的Datasheet PDF文件第4页浏览型号CXK79M36C160GB-4的Datasheet PDF文件第5页浏览型号CXK79M36C160GB-4的Datasheet PDF文件第6页浏览型号CXK79M36C160GB-4的Datasheet PDF文件第7页 
SONY ΣRAMCXK79M72C160GB / CXK79M36C160GB 33/4/5  
18Mb 1x1Lp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)  
Preliminary  
Description  
The CXK79M72C160GB (organized as 262,144 words by 72 bits) and the CXK79M36C160GB (organized as 524,288 words  
by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with  
the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAMdevices. They integrate input registers, high speed  
RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read  
operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive and neg-  
ative output clocks are provided for applications requiring source-synchronous operation.  
All address and control input signals are registered on the rising edge of the CK differential input clock.  
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control  
signals are registered.  
During write operations, input data is registered once, on the rising edge of CK, one full cycle after the address and control  
signals are registered.  
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor  
RQ is connected between ZQ and VSS, the impedance of the SRAM’s output drivers is set to ~RQ/5.  
300 MHz operation (300 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using  
a subset of IEEE standard 1149.1 protocol.  
Features  
3 Speed Bins  
Cycle Time / Data Access Time  
3.3ns / 1.8ns  
-33  
-4  
4.0ns / 2.1ns  
-5  
5.0ns / 2.3ns  
• Single 1.8V power supply (VDD): 1.7V (min) to 1.95V (max)  
• Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max)  
• HSTL-compatible I/O interface with dedicated input reference voltage (VREF): VDDQ/2 typical  
• Common I/O  
• Single Data Rate (SDR) data transfers  
• Pipelined (PL) read operations  
• Late Write (LW) write operations  
• Burst capability with internally controlled Linear Burst address sequencing  
• Burst length of two, three, or four, with automatic address wrap  
• Full read/write data coherency  
• Byte write capability  
• Differential input clocks (CK and CK)  
• Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)  
• Programmable output driver impedance via dedicated control pin (ZQ)  
• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)  
• JTAG boundary scan (subset of IEEE standard 1149.1)  
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
18Mb 1x1Lp, HSTL, rev 1.1  
1 / 28  
November 8, 2002  

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