Datasheet > CXK77P36L80AGB

CXK77P36L80AGB

更新时间： 2024-09-19 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
25页	271K
描述
MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (25 pages 270K Rev. 5/22/02)

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CXK77P36L80AGB 数据手册

SONYÒ CXK77P36L80AGB / CXK77P18L80AGB 4/42/43/44

8Mb LW R-L HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x18)

Preliminary

Description

The CXK77P36L80AGB (organized as 262,144 words by 36 bits) and the CXK77P18L80AGB (organized as 524,288 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read

operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K

(Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

•

Single 3.3V power supply (V ): 3.3V ± 5%

Dedicated output supply voltage (V

): 1.5V typical

DDQ

Extended HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.75V typical

REF

Late Write (LW) write operations

Full read/write coherency

Byte Write capability

Differential input clocks (K/K)

Asynchronous output enable (G)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

8Mb LW R-L, rev 1.1

1 / 25

May 22, 2002

12 3 4 5 6 7...25

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与CXK77P36L80AGB相关器件

型号	品牌	获取价格	描述	数据表
CXK77P36L80AGB-4	SONY	获取价格	Late-Write SRAM, 256KX36, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-42A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-42B	SONY	获取价格	Late-Write SRAM, 256KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
CXK77P36L80AGB-43	SONY	获取价格	Late-Write SRAM, 256KX36, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-43A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-43B	SONY	获取价格	Late-Write SRAM, 256KX36, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-44	SONY	获取价格	Late-Write SRAM, 256KX36, 4.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-4A	SONY	获取价格	Late-Write SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80GB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 8Meg Ultra-Hig
CXK77P36L80GB-42A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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