生命周期: | Contact Manufacturer | 包装说明: | SOP, |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.67 | Is Samacsys: | N |
系列: | HC/UH | JESD-30 代码: | R-PDSO-G14 |
长度: | 8.65 mm | 逻辑集成电路类型: | NAND GATE |
功能数量: | 3 | 输入次数: | 3 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SOP | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 传播延迟(tpd): | 150 ns |
座面最大高度: | 1.75 mm | 最大供电电压 (Vsup): | 6 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 4.5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | MILITARY | 端子形式: | GULL WING |
端子节距: | 1.27 mm | 端子位置: | DUAL |
宽度: | 3.9 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD74HC11 | TI |
获取价格 |
High Speed CMOS Logic Triple 3-Input AND Gate | |
CD74HC112 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD74HC112E | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD74HC112EE4 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD74HC112EE4 | ROCHESTER |
获取价格 |
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, | |
CD74HC112EN | ETC |
获取价格 |
Logic IC | |
CD74HC112EX | RENESAS |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC | |
CD74HC112F | ETC |
获取价格 |
Logic IC | |
CD74HC112H | ETC |
获取价格 |
J-K-Type Flip-Flop | |
CD74HC112M | ROCHESTER |
获取价格 |
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, |