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CD74HC112PWR PDF预览

CD74HC112PWR

更新时间： 2024-10-31 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 346K
描述
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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CD74HC112PWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.11Samacsys Description：High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
系列：HCJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：J-K FLIP-FLOP
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.006 A
湿度敏感等级：1位数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：2/6 V最大电源电流（ICC）：0.04 mA
Prop。Delay @ Nom-Sup：53 ns传播延迟（tpd）：265 ns
认证状态：Not Qualified施密特触发器：No
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：NEGATIVE EDGE
宽度：4.4 mm最小 fmax：23 MHz

CD74HC112PWR 数据手册

 浏览型号CD74HC112PWR的Datasheet PDF文件第2页浏览型号CD74HC112PWR的Datasheet PDF文件第3页浏览型号CD74HC112PWR的Datasheet PDF文件第4页浏览型号CD74HC112PWR的Datasheet PDF文件第5页浏览型号CD74HC112PWR的Datasheet PDF文件第6页浏览型号CD74HC112PWR的Datasheet PDF文件第7页 
CD54HC112, CD74HC112,  
CD54HCT112, CD74HCT112  
Data sheet acquired from Harris Semiconductor  
SCHS141H  
Dual J-K Flip-Flop with Set and Reset  
Negative-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC112 and ’HCT112 utilize silicon-gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC112  
,
CD74  
HCT11  
2)  
• Asynchronous Set and Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Set, Reset, and  
Clock inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Set and Reset  
are accomplished asynchronously by low-level inputs.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
The HCT logic family is functionally as well as pin-  
compatible with the standard LS logic family.  
/Sub-  
ject  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
.
(Dual  
J-K  
Flip-  
Flop  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC112F3A  
CD54HCT112F3A  
CD74HC112E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
with  
• HC Types  
Setand  
Reset  
Nega-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC112MT  
CD74HC112M96  
CD74HC112NSR  
CD74HC112PW  
CD74HC112PWR  
CD74HC112PWT  
CD74HCT112E  
16 Ld SOIC  
at V  
= 5V  
CC  
16 Ld SOIC  
• HCT Types  
16 Ld SOP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Pinout  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CD54HC112, CD54HCT112 (CERDIP)  
CD74HC112 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT112 (PDIP)  
TOP VIEW  
1CP  
1K  
1
2
3
4
5
6
7
8
16 V  
CC  
15 1R  
14 2R  
13 2CP  
12 2K  
11 2J  
10 2S  
1J  
1S  
1Q  
1Q  
2Q  
9
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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中文翻译

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CD74HC112PWR 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC112PWRE4 TI

类似代替

 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWT TI

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 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PW TI

类似代替

 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

与CD74HC112PWR相关器件

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CD74HC112PWRE4 TI

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 		Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWRG4 TI

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 		Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWT TI

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 		Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWTE4 TI

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 		Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWTG TI

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 		IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,TSSOP,16PIN,PLASTIC
CD74HC112PWTG4 TI

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 		Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC11E TI

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 		High Speed CMOS Logic Triple 3-Input AND Gate
CD74HC11E RENESAS

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 		HC/UH SERIES, TRIPLE 3-INPUT AND GATE, PDIP14
CD74HC11E ROCHESTER

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 		AND Gate, HC/UH Series, 3-Func, 3-Input, CMOS, PDIP14, PACKAGE-14
CD74HC11EE4 TI

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 		High-Speed CMOS Logic Triple 3-Input AND Gate

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