CD74HC112E

更新时间： 2024-01-24 07:51:34

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器逻辑集成电路光电二极管
页数	文件大小	规格书
8页	57K
描述
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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技术参数
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CD74HC112E 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G16	负载电容（CL）：	50 pF
逻辑集成电路类型：	J-K FLIP-FLOP	最大频率@ Nom-Sup：	20000000 Hz
最大I（ol）：	0.004 A	功能数量：	2
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TAPE AND REEL	电源：	2/6 V
认证状态：	Not Qualified	子类别：	FF/Latches
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
触发器类型：	NEGATIVE EDGE	Base Number Matches：	1

CD74HC112E 数据手册

CD74HC112,

CD74HCT112

Data sheet acquired from Harris Semiconductor

SCHS141

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

March 1998

at V

= 5V

Features

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

[ /Title

(CD74

HC112

CD74

HCT11

V = 0.8V (Max), V = 2V (Min)

IL IH

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

Description

The Harris CD74HC112 and CD74HCT112 utilize silicon-

gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

/Sub-

ject

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

(Dual

J-K

• Fanout (Over Temperature Range)

These ﬂip-ﬂops have independent J, K, Set, Reset, and

Clock inputs and Q and Q outputs. They change state on the

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

Flip-

Flop

with

Setand

Reset

Nega-

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads negative-going transition of the clock pulse. Set and Reset

are accomplished asynchronously by low-level inputs.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

The 74HCT logic family is functionally as well as pin-

compatible with the standard 74LS logic family.

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

Ordering Information

• HC Types

TEMP. RANGE

PKG.

NO.

- 2V to 6V Operation

PART NUMBER

( C)

PACKAGE

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC112E

-55 to 125

16 Ld PDIP

E16.3

Pinout

CD74HC112, CD74HCT112

(PDIP)

TOP VIEW

1CP

16 V

15 1R

14 2R

13 2CP

12 2K

11 2J

10 2S

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1843.1

12 3 4 5 6 7 8

中文翻译

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CD74HC112E 替代型号

型号	品牌	替代类型	描述	数据表
CD54HCT112F3A	TI	完全替代	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
SN74HC112N	TI	类似代替	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC109N	TI	类似代替	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与CD74HC112E相关器件

型号	品牌	获取价格	描述	数据表
CD74HC112EE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112EE4	ROCHESTER	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
CD74HC112EN	ETC	获取价格	Logic IC
CD74HC112EX	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC
CD74HC112F	ETC	获取价格	Logic IC
CD74HC112H	ETC	获取价格	J-K-Type Flip-Flop
CD74HC112M	ROCHESTER	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
CD74HC112M96	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112M96	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,16PIN,PLASTIC
CD74HC112M96E4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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