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CD74HC112EE4 PDF预览

CD74HC112EE4

更新时间： 2024-11-01 20:27:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
20页 755K
描述
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16

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CD74HC112EE4 技术参数

生命周期：Contact Manufacturer包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.59Is Samacsys：N
系列：HC/UHJESD-30 代码：R-PDIP-T16
长度：19.305 mm逻辑集成电路类型：J-K FLIP-FLOP
位数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：265 ns座面最大高度：5.08 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：NEGATIVE EDGE
宽度：7.62 mm最小 fmax：23 MHz
Base Number Matches：1

CD74HC112EE4 数据手册

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CD54HC112, CD74HC112,  
CD54HCT112, CD74HCT112  
Data sheet acquired from Harris Semiconductor  
SCHS141H  
Dual J-K Flip-Flop with Set and Reset  
Negative-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC112 and ’HCT112 utilize silicon-gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC112  
,
CD74  
HCT11  
2)  
• Asynchronous Set and Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Set, Reset, and  
Clock inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Set and Reset  
are accomplished asynchronously by low-level inputs.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
The HCT logic family is functionally as well as pin-  
compatible with the standard LS logic family.  
/Sub-  
ject  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
.
(Dual  
J-K  
Flip-  
Flop  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC112F3A  
CD54HCT112F3A  
CD74HC112E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
with  
• HC Types  
Setand  
Reset  
Nega-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC112MT  
CD74HC112M96  
CD74HC112NSR  
CD74HC112PW  
CD74HC112PWR  
CD74HC112PWT  
CD74HCT112E  
16 Ld SOIC  
at V  
= 5V  
CC  
16 Ld SOIC  
• HCT Types  
16 Ld SOP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Pinout  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CD54HC112, CD54HCT112 (CERDIP)  
CD74HC112 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT112 (PDIP)  
TOP VIEW  
1CP  
1K  
1
2
3
4
5
6
7
8
16 V  
CC  
15 1R  
14 2R  
13 2CP  
12 2K  
11 2J  
10 2S  
1J  
1S  
1Q  
1Q  
2Q  
9
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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