Datasheet > CD74HC112NSR96

CD74HC112NSR96

更新时间： 2024-10-31 23:41:15

品牌	Logo	应用领域
其他 - ETC		触发器
页数	文件大小	规格书
8页	45K
描述
FLIP-FLOP\|DUAL\|J/K TYPE\|HC-CMOS\|SOP\|16PIN\|PLASTIC

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数据手册

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CD74HC112NSR96 数据手册

CD54/74HC112,

CD54/74HCT112

Data sheet acquired from Harris Semiconductor

SCHS141B

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

March 1998 - Revised March 2002

Features

Description

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

The ’HC112 and ’HCT112 utilize silicon-gate CMOS

technology to achieve operating speeds equivalent to LSTTL

parts. They exhibit the low power consumption of standard

CMOS integrated circuits, together with the ability to drive 10

LSTTL loads.

[ /Title

(CD74

HC112

CD74

HCT11

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Set, Reset, and

Clock inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Set and Reset

are accomplished asynchronously by low-level inputs.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

The HCT logic family is functionally as well as pin-

compatible with the standard LS logic family.

/Sub-

ject

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

(Dual

J-K

Flip-

Flop

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC112F3A

CD74HC112E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

with

• HC Types

Setand

Reset

Nega-

- 2V to 6V Operation

CD74HC112NSR

CD54HCT112F3A

CD74HCT112E

NOTES:

16 Ld SOP

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

16 Ld CERDIP

16 Ld PDIP

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

2. Wafer and die is available which meets all electrical specifica-

tions. Please contact your local TI sales office or customer ser-

vice for ordering information.

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

CD54HC112, CD54HCT112

(CERDIP)

CD74HC112

(PDIP, SOP)

CD74HCT112

(PDIP)

TOP VIEW

1CP

16 V

15 1R

14 2R

13 2CP

12 2K

11 2J

10 2S

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7 8

中文翻译

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与CD74HC112NSR96相关器件

型号	品牌	获取价格	描述	数据表
CD74HC112NSRE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112NSRE4	ROCHESTER	获取价格	J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output,
CD74HC112NSRG4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PW	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWG4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWR	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWRE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWRG4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HC112PWT	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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