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BUK9830-30 PDF预览

BUK9830-30

更新时间: 2024-11-12 22:32:31
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管功率场效应晶体管开关脉冲光电二极管
页数 文件大小 规格书
10页 59K
描述
TrenchMOS transistor Logic level FET

BUK9830-30 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PDSO-G4
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8541.29.00.95风险等级:5.84
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED
雪崩能效等级(Eas):60 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:30 V
最大漏极电流 (ID):5.9 A最大漏源导通电阻:0.03 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-G4
元件数量:1端子数量:4
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):23.6 A
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

BUK9830-30 数据手册

 浏览型号BUK9830-30的Datasheet PDF文件第2页浏览型号BUK9830-30的Datasheet PDF文件第3页浏览型号BUK9830-30的Datasheet PDF文件第4页浏览型号BUK9830-30的Datasheet PDF文件第5页浏览型号BUK9830-30的Datasheet PDF文件第6页浏览型号BUK9830-30的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
BUK9830-30  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode logic  
level field-effect power transistor in a  
plastic envelope suitable for surface  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Drain-source voltage  
30  
12.8  
5.9  
8.3  
150  
30  
V
A
A
W
˚C  
m  
mounting.  
Using  
trench’  
Drain current (DC) Tsp = 25 ˚C  
Drain current (DC) Tamb = 25 ˚C  
Total power dissipation  
Junction temperature  
Drain-source on-state  
resistance  
technology, the device features very  
low on-state resistance and has  
integral zener diodes giving ESD  
protection up to 2kV. It is intended for  
use in automotive and general  
purpose switching applications.  
Ptot  
Tj  
RDS(ON)  
VGS = 5 V  
PINNING - SOT223  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
4
gate  
2
drain  
g
3
source  
4
drain (tab)  
s
2
3
1
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
Drain-source voltage  
-
-
-
-
-
-
-
-
-
30  
30  
10  
12.8  
5.9  
9
4.1  
51  
23.6  
8.3  
1.8  
150  
V
V
V
A
A
A
A
A
A
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
RGS = 20 kΩ  
-
Tsp = 25 ˚C  
Tamb = 25 ˚C  
Tsp = 100 ˚C  
Tamb = 100 ˚C  
Tsp = 25 ˚C  
Tamb = 25 ˚C  
Tsp = 25 ˚C  
Tamb = 25 ˚C  
-
ID  
Drain current (DC)  
IDM  
Drain current (pulse peak value)  
Total power dissipation  
-
-
-
Ptot  
W
W
˚C  
Tstg, Tj  
Storage & operating temperature  
- 55  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-sp  
Thermal resistance junction to  
solder point  
Mounted on any PCB  
12  
15  
K/W  
Rth j-amb  
Thermal resistance junction to  
ambient  
Mounted on PCB of Fig.19  
-
70  
K/W  
December 1997  
1
Rev 1.100  

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