DRAM
AS4LC4M16
Austin Semiconductor, Inc.
4 MEG x 16 DRAM
PIN ASSIGNMENT
Extended Data Out (EDO) DRAM
(TopView)
50-Pin TSOP (DG)
FEATURES
• Single +3.3V ±0.3V power supply.
• Industry-standard x16 pinout, timing, functions, and
package.
• 12 row, 10 column addresses
• High-performance CMOS silicon-gate process
•All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data retention
• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020
OPTIONS
• Package(s)
MARKINGS
50-pin TSOP (400-mil)
DG
• Timing
50ns access
-5
-6
60ns access
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
A0-A11
A0-A9
• Refresh Rates
Standard Refresh
Self Refresh
None
S*
• Operating Temperature Ranges
Military (-55°C to +125°C)
Industrial (-40°C to +85°C)
XT
IT
NOTE: The \ symbol indicates signal is active LOW.
*Contact factory for availability. Self refresh option available on IT
version only.
For more products and information
please visit our web site at
www.austinsemiconductor.com
KEY TIMING PARAMETERS
tRC
tRAC
tPC
tAA
tCAC tCAS
SPEED
-5
-6
84ns 50ns 20ns 25ns 13ns 8ns
104ns 60ns 25ns 30ns 15ns 10ns
AS4LC4M16
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 6/05
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