Advance information
AS4LC8M8S0
AS4LC4M16S0
®
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
• PC100/ 133 compliant
• Organization
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/ O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 54-pin TSOP II
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
- All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/ BA1 (bank select)
• High speed
- 133/ 125/ 100 MHz
- 5.4 ns (133 MHz)/ 6 ns (125/ 100 MHz) clock access time
• Low power consumption
• Read/ write data masking
• Programmable burst length (1/ 2/ 4/ 8/ full page)
• Programmable burst sequence (sequential/ interleaved)
• Programmable CAS latency (2/ 3)
- Standby: 7.2 mW max, CMOS I/ O
Pin designation
Pin arrangement
AS4LC4M16S0
Pin(s)
Description
V
V
SS
DQ7
V
V
DQM (8M×8)
UDQM/ LDQM (4M×16)
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
CC
DQ0
CC
SS
Output disable/ write mask
DQ0
DQ15
V
V
V
CCQ
V
CCQ
SSQ
SSQ
NC
DQ1
DQ1
DQ2
DQ14
DQ13
NC
DQ6
A0 to A11
BA0, BA1
Address inputs
V
V
V
V
CCQ
CCQ
SSQ
SSQ
Bank select inputs
NC
DQ3
DQ4
DQ12
DQ11
NC
DQ5
DQ2
V
V
DQ0 to DQ7 (8M×8)
DQ0 to DQ15 (4M×16)
CCQ
CCQ
V
V
9
SSQ
SSQ
Input/ output
NC
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ10
DQ9
NC
DQ4
DQ3
V
V
V
V
SSQ
SSQ
CCQ
CCQ
RAS
CAS
Row address strobe
Column address strobe
Write enable
NC
DQ7
DQ8
NC
V
V
V
V
CC
SS
CC
SS
NC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
39
38
37
36
35
34
33
DQM
CLK
CKE
WE
CS
Chip select
NC
A11
A9
A8
A7
A6
A5
A4
VCC, VCCQ
Power (3.3V ± 0.3V)
Ground
23
24
25
26
27
V , V
32
31
30
29
28
SS SSQ
A1
A2
A3
A1
A2
CLK
CKE
Clock input
A3
A4
V
V
V
SS
V
CC
CC
SS
Clock enable
AS4LC4M16S0
Selection guide
Symbol -75 (PC133)
-8
-10F (PC100) -10 (PC100)
Unit
Bus frequency
fmax
tAC
tAC
tS
133
–
125
100
100
MHz
ns
CL = 2
CL = 3
–
6
–
Minimum clock access time
5.4
1.5
0.8
3
6
–
6
ns
Minimum setup time
2
1.0
3
2
1.0
2
2
1.0
3
ns
Minimum hold time
tH
ns
Minimum RAS to CAS delay
Minimum RAS precharge time
Remarks: (CL/ tRCD/ tRP)
tRCD
tRP
cycles
cycles
3
3
2
3
3/ 3/ 3
3/ 3/ 3
2/ 2/ 2
3/ 3/ 3
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
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