Datasheet > AS4LC4M16DG-5S/XT

AS4LC4M16DG-5S/XT

更新时间： 2024-11-11 06:37:51

品牌	Logo	应用领域
AUSTIN		动态存储器
页数	文件大小	规格书
25页	520K
描述
4 MEG x 16 DRAM

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中文翻译

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数据手册

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DRAM

AS4LC4M16

Austin Semiconductor, Inc.

4 MEG x 16 DRAM

PIN ASSIGNMENT

Extended Data Out (EDO) DRAM

(Top View)

50-Pin TSOP (DG)

FEATURES

• Single +3.3V ±0.3V power supply.

• Industry-standard x16 pinout, timing, functions, and

package.

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• Extended Data-Out (EDO) PAGE MODE access

• 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH

distributed across 64ms

• Optional self refresh (S) for low-power data retention

• Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020

OPTIONS

• Package(s)

MARKINGS

50-pin TSOP (400-mil)

• Timing

50ns access

-5

-6

60ns access

Configuration

Refresh

Row Address

Column Addressing

4 Meg x 16

A0-A11

A0-A9

• Refresh Rates

Standard Refresh

Self Refresh

None

• Operating Temperature Ranges

Military (-55°C to +125°C)

Industrial (-40°C to +85°C)

NOTE: The \ symbol indicates signal is active LOW.

*Contact factory for availability. Self refresh option available on IT

version only.

For more products and information

please visit our web site at

www.austinsemiconductor.com

KEY TIMING PARAMETERS

t_RC

t_RAC

t_PC

t_AA

t_CACt_CAS

SPEED

-5

-6

84ns 50ns 20ns 25ns 13ns 8ns

104ns 60ns 25ns 30ns 15ns 10ns

AS4LC4M16

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 7/02

12 3 4 5 6 7...25

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与AS4LC4M16DG-5S/XT相关器件

型号	品牌	获取价格	描述	数据表
AS4LC4M16DG-6/IT	MICROSS	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50,
AS4LC4M16DG-6/XT	MICROSS	获取价格	EDO DRAM, 4MX16, 60ns, CMOS, PDSO50, 0.400 INCH, TSOP-50
AS4LC4M16DG-6S/IT	AUSTIN	获取价格	4 MEG x 16 DRAM Extended Data Out (EDO) DRAM
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