March 2001
AS4LC4M4E0
AS4LC4M4E1
®
4Mx4 CMOS DRAM (EDO) Family
Features
• Refresh
• Organization: 4,194,304 words × 4 bits
- 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0
- 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Extended data out
• 3V power supply
• Industrial and commercial temperature available
Pin designation
Pin arrangement
Pin(s)
A0 to A11
Description
Address inputs
SOJ
TSOP
VCC
GND
I/O3
I/O2
CAS
OE
VCC
GND
I/O3
I/O2
CAS
OE
1
2
3
4
5
6
24
23
22
21
20
19
1
2
3
4
5
6
24
23
22
21
20
19
I/O0
I/O1
WE
I/O0
I/O1
WE
RAS
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
CAS
RAS
RAS
*NC/A11
A9 *NC/A11
A9
WE
A10
A8
A7
A6
A5
A4
GND
A10
A8
A7
A6
A5
A4
I/O0 to I/O3
7
8
9
10
11
12
18
17
16
15
14
13
7
8
9
10
11
12
18
17
16
15
14
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
OE
VCC
GND
13 GND
Ground
* NC on 2K refresh version; A11 on 4K refresh version
Selection guide
Symbol AS4LC4M4E0/E1-50 AS4LC4M4E0/E1-60 Unit
Maximum RAS access time
tRAC
tCAA
tCAC
tOEA
tRC
50
25
12
13
80
25
120
1.0
60
ns
Maximum column address access time
Maximum CAS access time
30
ns
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
15
ns
100
30
ns
tPC
ns
ICC1
ICC5
110
1.0
mA
mA
Maximum CMOS standby current
4/11/01; V.1.1
Alliance Semiconductor
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