Datasheet > AS4LC4M4E1-50TI

AS4LC4M4E1-50TI

更新时间： 2024-11-10 23:31:35

品牌	Logo	应用领域
其他 - ETC		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
15页	276K
描述
x4 EDO Page Mode DRAM

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中文翻译

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数据手册

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AS4LC4M4E1-50TI 数据手册

May 2001

AS4LC4M4E1

4Mx4 CMOS DRAM (EDO)3.3V Family

Features

• Refresh

• Organization: 4,194,304 words × 4 bits

- 2048 refresh cycles, 32 ms refresh interval

- RAS-only or CAS-before-RAS refresh or self-refresh

• TTL-compatible, three-state I/O

• JEDEC standard package

- 300 mil, 24/26-pin SOJ

• 3.3V power supply

• High speed

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS access time

• Low power consumption

- Active: 500 mW max

- Standby: 3.6 mW max, CMOS I/O

• Extended data out

• ESD protection 2000 V

≥

• Latch-current 200 mA

≥

• Industrial and commercial temperature available

Pin arrangement

Pin designation

SOJ

TSOP

Pin(s)

A0 to A10

Description

V_CC

GND

I/O3

I/O2

CAS

V_CC

GND

I/O3

I/O2

CAS

I/O0

I/O1

RAS

I/O0

I/O1

RAS

Address inputs

Row address strobe

Column address strobe

Write enable

Input/output

Output enable

Power

RAS

CAS

A10

GND

A10

V_CC

I/O0 to I/O3

V_CC

GND

13 GND

Ground

*TSOP availability to be determined.

Selection guide

Symbol AS4LC4M4E1-50

AS4LC4M4E1-60

Unit

Maximum RAS access time

t_RAC

t_CAA

t_CAC

t_OEA

t_RC

120

1.0

Maximum column address access time

Maximum CAS access time

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum fast page mode cycle time

Maximum operating current

100

t_PC

I_CC1

I_CC5

110

1.0

Maximum CMOS standby current

5/1/01; V.1.3

Alliance Semiconductor

P. 1 of 15

12 3 4 5 6 7...15

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