Datasheet > 存储 > DRAM> AS4LC4M4F1-60TI

AS4LC4M4F1-60TI

更新时间： 2024-11-11 08:35:07

品牌	Logo	应用领域
ALSC		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
14页	269K
描述
4M×4 CMOS DRAM (Fast Page) 3.3V Family

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数据手册

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AS4LC4M4F1-60TI 数据手册

May 2001

AS4LC4M4F1

4M×4 CMOS DRAM (Fast Page) 3.3V Family

Features

• Refresh

• Organization: 4,194,304 words × 4 bits

- 2048 refresh cycles, 32 ms refresh interval

- RAS-only or CAS-before-RAS refresh or self-refresh

• TTL-compatible, three-state I/O

• JEDEC standard package

- 300 mil, 24/26-pin SOJ

• 3.3V power supply

• High speed

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS access time

• Low power consumption

- Active: 500 mW max

- Standby: 3.6 mW max, CMOS I/O

• Fast page mode

• Latch-up current ≥ 200 mA

• ESD protection ≥ 2000 volts

• Industrial and commercial temperature available

Pin arrangement

Pin designation

Pin(s)

A0 to A10

RAS

Description

SOJ

TSOP*

Address inputs

Row address strobe

Column address strobe

Write enable

Input/output

Output enable

Power

V_CC

GND

I/O3

I/O2

CAS

V_CC

GND

I/O3

I/O2

CAS

I/O0

I/O1

RAS

I/O0

I/O1

RAS

CAS

A10

GND

I/O0 to I/O3

V_CC

GND

Ground

*TSOP availability to be determined

Selection guide

Symbol

AS4LC4M4F1-50

AS4LC4M4F1-60

Unit

Maximum RAS access time

t_RAC

t_CAA

t_CAC

t_OEA

t_RC

Maximum column address access time

Maximum CAS access time

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum fast page mode cycle time

Maximum operating current

100

t_PC

I_CC1

I_CC5

120

1.0

110

1.0

Maximum CMOS standby current

5/16/01; v.1.0 Restored

Alliance Semiconductor

P. 1 of 14

12 3 4 5 6 7...14

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