May 2001
AS4LC4M4F1
®
4M×4 CMOS DRAM (Fast Page) 3.3V Family
Features
• Refresh
• Organization: 4,194,304 words × 4 bits
- 2048 refresh cycles, 32 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3.3V power supply
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Fast page mode
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 volts
• Industrial and commercial temperature available
Pin arrangement
Pin designation
Pin(s)
A0 to A10
RAS
Description
SOJ
TSOP*
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
VCC
GND
I/O3
I/O2
CAS
OE
VCC
GND
I/O3
I/O2
CAS
OE
1
2
3
4
5
6
26
25
24
23
22
21
1
2
3
4
5
6
19
18
17
16
15
14
I/O0
I/O1
WE
RAS
NC
I/O0
I/O1
WE
RAS
NC
CAS
A9
A9
WE
A10
A8
A7
A6
A5
A4
A10
A8
A7
A6
A5
A4
GND
8
9
I/O0 to I/O3
OE
8
9
10
11
12
13
19
18
17
16
15
14
26
25
24
23
22
21
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
10
11
12
13
VCC
GND
GND
Ground
*TSOP availability to be determined
Selection guide
Symbol
AS4LC4M4F1-50
AS4LC4M4F1-60
Unit
ns
Maximum RAS access time
tRAC
tCAA
tCAC
tOEA
tRC
50
25
60
30
Maximum column address access time
Maximum CAS access time
ns
12
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
13
15
ns
80
100
30
ns
tPC
25
ns
ICC1
ICC5
120
1.0
110
1.0
mA
mA
Maximum CMOS standby current
5/16/01; v.1.0 Restored
Alliance Semiconductor
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