Ultrafast SiGe
ECL Clock/Data Buffers
Data Sheet
ADCLK905/ADCLK907/ADCLK925
FEATURES
TYPICAL APPLICATION CIRCUITS
V
V
REF
CC
95 ps propagation delay
V
T
7.5 GHz toggle rate
60 ps typical output rise/fall
D
D
Q
Q
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC − VEE
)
V
EE
APPLICATIONS
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
V
1
REF
V 1
T
V
CC
Threshold detection
D1
D1
Q1
Q1
Converter clocking
V
V
EE
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
EE
D2
D2
Q2
Q2
V
CC
V 2
T
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
V
2
REF
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
V
EE to the negative supply.
V
REF
V
CC
V
T
Q1
Q1
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
D
D
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
Q2
Q2
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
V
EE
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
Rev. B
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