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ADCLK925BCPZ-WP PDF预览

ADCLK925BCPZ-WP

更新时间: 2024-11-27 12:53:19
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
16页 1104K
描述
Ultrafast SiGe ECL Clock/Data Buffers

ADCLK925BCPZ-WP 数据手册

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Ultrafast SiGe  
ECL Clock/Data Buffers  
ADCLK905/ADCLK907/ADCLK925  
FEATURES  
TYPICAL APPLICATION CIRCUITS  
95 ps propagation delay  
V
7.5 GHz toggle rate  
60 ps typical output rise/fall  
REF  
V
CC  
V
T
60 fs random jitter (RJ)  
D
D
Q
Q
On-chip terminations at both input pins  
Extended industrial temperature range: −40°C to +125°C  
2.5 V to 3.3 V power supply (VCC VEE)  
APPLICATIONS  
V
EE  
Clock and data signal restoration and level shifting  
Automated test equipment (ATE)  
High speed instrumentation  
High speed line receivers  
Threshold detection  
Converter clocking  
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer  
V
1
REF  
V 1  
T
V
V
CC  
GENERAL DESCRIPTION  
D1  
D1  
Q1  
Q1  
The ADCLK905 (one input, one output), ADCLK907 (dual one  
input, one output), and ADCLK925 (one input, two outputs) are  
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,  
proprietary XFCB3 silicon germanium (SiGe) bipolar process.  
EE  
V
EE  
D2  
D2  
Q2  
Q2  
The ADCLK905/ADCLK907/ADCLK925 feature full-swing  
emitter coupled logic (ECL) output drivers. For PECL (positive  
ECL) operation, bias VCC to the positive supply and VEE to ground.  
For NECL (negative ECL) operation, bias VCC to ground and  
V
CC  
V 2  
T
V
2
REF  
VEE to the negative supply.  
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer  
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,  
10 Gbps data rate, and 60 fs random jitter (RJ).  
The inputs have center tapped, 100 Ω, on-chip termination  
resistors. A VREF pin is available for biasing ac-coupled inputs.  
V
REF  
V
CC  
V
T
Q1  
Q1  
The ECL output stages are designed to directly drive 800 mV  
each side into 50 Ω terminated to VCC − 2 V for a total  
differential output swing of 1.6 V.  
D
D
Q2  
Q2  
The ADCLK905/ADCLK907/ADCLK925 are available in  
16-lead LFCSP packages.  
V
EE  
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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