5秒后页面跳转
8T73S1802NLGI PDF预览

8T73S1802NLGI

更新时间: 2024-12-01 01:07:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
25页 816K
描述
1:2 Clock Fanout Buffer and Frequency Divider

8T73S1802NLGI 数据手册

 浏览型号8T73S1802NLGI的Datasheet PDF文件第2页浏览型号8T73S1802NLGI的Datasheet PDF文件第3页浏览型号8T73S1802NLGI的Datasheet PDF文件第4页浏览型号8T73S1802NLGI的Datasheet PDF文件第5页浏览型号8T73S1802NLGI的Datasheet PDF文件第6页浏览型号8T73S1802NLGI的Datasheet PDF文件第7页 
1:2 Clock Fanout Buffer and  
Frequency Divider  
8T73S1802  
Datasheet  
General Description  
Features  
The 8T73S1802 is a fully integrated clock fanout buffer and  
frequency divider. The input signal is frequency-divided and then  
fanned out to one differential LVPECL and one LVCMOS output.  
Each of the outputs can select its individual divider value from the  
range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and  
SEL1 (3-level logic) are available to select the frequency dividers  
and the output enable/disable state. The single-ended LVCMOS  
output is phase-delayed by 650ps to minimize coupling of  
LVCMOS switching into the differential output during its signal  
transition.  
• High-performance fanout buffer clock and fanout buffer  
• Input clock signal is distributed to one LVPECL and one  
LVCMOS output  
• Configurable output dividers for both LVPECL and LVCMOS  
outputs  
• Supports clock frequencies up to 1000MHz (LVPECL) and up to  
200MHz (LVCMOS)  
• Flexible differential input supports LVPECL, LVDS and CML  
• VBB generator output supports single-ended input signal  
applications  
The 8T73S1802 is optimized to deliver very low phase noise  
clocks. The VBB output generates a common-mode voltage  
reference for the differential clock input so that connecting the VBB  
pin to an unused input (nCLK) enables to use of single-ended input  
signals. The extended temperature range supports wireless  
infrastructure, telecommunication and networking end equipment  
requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V  
power supply. The device is a member of the high-performance  
clock family from IDT.  
• Optimized for low phase noise  
• 650ps delay between LVCMOS and LVPECL minimizes coupling  
between outputs  
• Supply voltage: 3.3V or 2.5V  
• -40°C to 85°C ambient operating temperature  
• 16 VFQFN package (3mm x 3mm)  
©2017 Integrated Device Technology, Inc.  
1
February 7, 2017  

与8T73S1802NLGI相关器件

型号 品牌 获取价格 描述 数据表
8T73S1802NLGI/W IDT

获取价格

1:2 Clock Fanout Buffer and Frequency Divider
8T73S1802NLGI8 IDT

获取价格

1:2 Clock Fanout Buffer and Frequency Divider
8T73S208 IDT

获取价格

2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T73S208 RENESAS

获取价格

2.5V/3.3V Differential LVPECL Clock Divider And Fanout Buffer
8T73S208_16 IDT

获取价格

2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T73S208A-01 IDT

获取价格

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer
8T73S208A-01_16 IDT

获取价格

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer
8T73S208A-01NLGI IDT

获取价格

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer
8T73S208A-01NLGI8 IDT

获取价格

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer
8T73S208B-01 IDT

获取价格

2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer