Datasheet > 8T73S208B-01

8T73S208B-01

更新时间： 2024-12-01 14:57:31

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
19页	585K
描述
2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

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8T73S208B-01 数据手册

8T73S208B-01

Datasheet

2.5 V, 3.3 V Differential LVPECL

Clock Divider and Fanout Buffer

General Description

Features

The 8T73S208B-01 is a high-performance differential LVPECL

clock divider and fanout buffer. The device is designed for the

frequency division and signal fanout of high-frequency, low

phase-noise clocks. The 8T73S208B-01 is characterized to

operate from a 2.5V and 3.3V power supply. Guaranteed

output-to-output and part-to-part skew characteristics make the

8T73S208B-01 ideal for those clock distribution applications

demanding well-defined performance and repeatability. The

integrated input termination resistors make interfacing to the

reference source easy and reduce passive component count.

Each output can be individually enabled or disabled in the

high-impedance state controlled by a I²C register. On power-up, all

outputs are disabled.

• One differential input reference clock

• Differential pair can accept the following differential input

levels: LVDS, LVPECL, CML

• Integrated input termination resistors

• Eight LVPECL outputs

• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

• Maximum input clock frequency: 1GHz

• LVCMOS interface levels for the control inputs

• Individual output enable/disabled by I²C interface

• Power-up state: all outputs disabled

• Output skew: 60ps (maximum)

• Output rise/fall times: 350ps (maximum)

• Low additive phase jitter, RMS: 182fs (typical)

• Full 2.5V and 3.3V supply voltages

• Lead-free (RoHS 6) 32-VFQFPN packaging

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

nQ0

31 30 29 28 27 26 25

nQ1

f_REF

ADR1

V_EE

FSEL0

V_EE

÷1, ÷2,

÷4, ÷8

nIN

nQ2

50

nQ7

V_T

nQ3

nQ0

Pulldown (2)

FSEL[1:0]

nQ6

nQ4

nQ1

V_EE

nQ5

Pullup

V_CCO

SDA

SCL

I²C

10 11 12 13 14 15 16

Pullup

Pulldown (2)

nQ6

ADR[1:0]

nQ7

5 × 5 mm, 32-VFQFPN

April 8, 2020

12 3 4 5 6 7...19

中文翻译

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与8T73S208B-01相关器件

型号	品牌	获取价格	描述	数据表
8T73S208B-01NLGI	IDT	获取价格	2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T73S208B-01NLGI8	IDT	获取价格	2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T73S208BNLGI	IDT	获取价格	2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T73S208BNLGI8	IDT	获取价格	2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer
8T74S208A-01	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208A-01_16	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208A-01NLGI	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208A-01NLGI8	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01	IDT	获取价格	2.5 V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01	RENESAS	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer

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