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8T73S208_16

更新时间： 2024-12-01 01:07:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 532K
描述
2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer

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8T73S208_16 数据手册

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2.5 V, 3.3 V Differential LVPECL  
Clock Divider and Fanout Buffer  
8T73S208  
Datasheet  
General Description  
Features  
The 8T73S208 is a high-performance differential LVPECL clock  
divider and fanout buffer. The device is designed for the frequency  
division and signal fanout of high-frequency, low phase-noise clocks.  
The 8T73S208 is characterized to operate from a 2.5V and 3.3V  
power supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the 8T73S208 ideal for those clock distribution  
applications demanding well-defined performance and repeatability.  
The integrated input termination resistors make interfacing to the  
reference source easy and reduce passive component count. Each  
output can be individually enabled or disabled in the high-impedance  
state controlled by a I2C register. On power-up, all outputs are  
enabled.  
• One differential input reference clock  
• Differential pair can accept the following differential input  
levels: LVDS, LVPECL, CML  
• Integrated input termination resistors  
• Eight LVPECL outputs  
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8  
• Maximum input clock frequency: 1000MHz  
• LVCMOS interface levels for the control inputs  
• Individual output enable/disabled by I2C interface  
• Output skew: 15ps (typical)  
• Output rise/fall times: 350ps (maximum)  
• Low additive phase jitter, RMS: 0.182ps (typical)  
• Full 2.5V and 3.3V supply voltages  
• Lead-free (RoHS 6) 32-Lead VFQFN packaging  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
Q0  
nQ0  
23 22 21 20 19 18 17  
Q1  
24  
nQ1  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
FSEL1  
IN  
nQ5  
Q5  
fREF  
IN  
nIN  
Q2  
nQ2  
÷1, ÷2,  
÷4, ÷8  
VT  
nQ4  
Q4  
50  
50  
Q3  
nQ3  
nIN  
VT  
8T73S208  
VCC  
nQ3  
Q3  
Pulldown (2)  
FSEL[1:0]  
Q4  
nQ4  
2
SDA  
SCL  
ADR0  
nQ2  
Q5  
nQ5  
Q2  
I2C  
Pullup  
SDA  
SCL  
ADR[1:0]  
1
2
3
4
5
6
7
8
Pullup  
8
Q6  
Pulldown (2)  
nQ6  
2
Q7  
nQ7  
32-pin, 5mm x 5mm VFQFN  
©2016 Integrated Device Technology, Inc.  
1
Revision D, June 15, 2016  
1234567...22

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