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8T74S208C-01 PDF预览

8T74S208C-01

更新时间: 2024-01-01 04:09:38
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 469K
描述
2.5 V Differential LVDS Clock Divider and Fanout Buffer

8T74S208C-01 数据手册

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2.5 V Differential LVDS Clock Divider  
and Fanout Buffer  
8T74S208C-01  
Datasheet  
General Description  
Features  
The 8T74S208C-01 is a high-performance differential LVDS clock  
divider and fanout buffer. The device is designed for the frequency  
division and signal fanout of high-frequency, low phase-noise clocks.  
The 8T74S208C-01 is characterized to operate from a 2.5V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the 8T74S208C-01 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. The integrated input termination resistors make  
interfacing to the reference source easy and reduce passive  
component count. Each output can be individually enabled or  
disabled in the high-impedance state controlled by a I2C register. On  
power-up, all outputs are disabled.  
One differential input reference clock  
Differential pair can accept the following differential input levels:  
LVDS, LVPECL, CML  
Integrated input termination resistors  
Eight LVDS outputs  
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8  
Maximum input clock frequency: 1GHz  
LVCMOS interface levels for the control inputs  
Individual output enabled/ disabled by I2C interface  
Output skew: 45ps (maximum)  
Output rise/fall times: 370ps (maximum)  
Low additive phase jitter, RMS: 96fs (typical)  
Full 2.5V supply voltage  
Outputs disabled at power-up  
Lead-free (RoHS 6) 32-Lead VFQFN packaging  
-40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
Q0  
nQ0  
31 30 29 28 27 26 25  
32  
Q1  
nQ1  
fREF  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
ADR1  
GND  
Q0  
FSEL0  
GND  
nQ7  
Q7  
IN  
÷1, ÷2,  
÷4, ÷8  
nIN  
Q2  
nQ2  
50  
50  
VT  
nQ0  
Q1  
Q3  
nQ3  
Pulldown (2)  
FSEL[1:0]  
nQ6  
Q6  
2
Q4  
nQ4  
nQ1  
GND  
VDDO  
GND  
VDDO  
Q5  
nQ5  
Pullup  
SDA  
I2C  
9
10 11 12 13 14 15 16  
Pullup  
8
SCL  
Q6  
nQ6  
Pulldown (2)  
ADR[1:0]  
2
Q7  
nQ7  
8T74S208C-01  
32-Lead VFQFN, 5mm x 5mm x 0.925mm  
©2016 Integrated Device Technology, Inc.  
1
August 22, 2016  

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