Datasheet > 8T79S828I-08

8T79S828I-08

更新时间： 2024-12-01 14:58:27

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
29页	789K
描述
1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer

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数据手册

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8T79S828I-08 数据手册

1-to-8 Differential to Universal Output

Clock Divider/Fanout Buffer

IDT8T79S828-08I

DATASHEET

General Description

Features

The IDT8T79S828-08I is a high performance, 1-to-8, differential input

to universal output clock divider and fanout buffer. The device is

designed for frequency-division and signal fanout of high-frequency

clock signals in applications requiring four different output

frequencies generated simultaneously. Each bank of two outputs has

a selectable divider value of ÷1 through ÷6 and ÷8. The

IDT8T79S828-08I is optimized for 3.3V and 2.5V supply voltages and

a temperature range of -40°C to 85°C. The device is packaged in a

space-saving 32-Lead VFQFN package.

• Four banks of two low skew outputs

• Selectable bank output divider values: ÷1 through ÷6 and ÷8

• Individual outputs remain as configured while serial loading new

device configurations

• One differential PCLK, nPCLK input

• PCLK, nPCLK input pair can accept the following differential input

levels: LVPECL, LVDS levels

• Maximum input frequency: 1.5GHz

• LVCMOS control inputs

• QXx ÷1 edge aligned to QXx ÷n edge

• Individual output divider control via serial interface

• Individual output enable/disable control via serial interface

• Individual output type control, LVDS or LVPECL, via serial

interface

• 2.375V to 3.465V supply voltage operation

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Block Diagram

Pin Assignment

VCC

QA0

nQA0

Pulldown

PCLK

nPCLK

Dividers

RST

Pullup/Pulldown

QA1

nQA1

V_CC25

V_EE26

16 V_CC

VEE

QB0

nQB0

15 V_EE

IDT8T79S828-08I

nQA1 27

QA1 28

nQA0 29

QA0 30

V_CC31

14 QD0

13 nQD0

12 QD1

11 nQD1

10 V_CC

QB1

nQB1

32 lead VFQFN

5mm x 5mm x 0.925mm

Pad size 3.15mm x 3.15mm

NL package

QC0

nQC0

Pulldown

PWR_SEL

QC1

nQC1

Top View

VEE

VCC

SDATA 32

PWR_SEL

QD0

nQD0

QD1

nQD1

Pullup

nRST

SCLK

SDATA

Pulldown

Divider Select,

O utput Type and

O utput Enable

logic

MISO

VEE VEE VEE VEE

IDT8T79S828-08NLGI REVISION A APRIL 22, 2014

12 3 4 5 6 7...29

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