Datasheet > 8T74S208A-01

8T74S208A-01

更新时间： 2024-12-01 01:07:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	367K
描述
2.5V Differential LVDS Clock Divider and Fanout Buffer

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数据手册

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8T74S208A-01 数据手册

2.5V Differential LVDS Clock Divider and

Fanout Buffer

8T74S208A-01

REFER TO PCN# N1608-01, Effective Date November 18, 2016

DATA SHEET

FOR NEW DESIGNS USE PART NUMBER 8T74S208C-01

General Description

Features

The 8T74S208A-01 is a high-performance differential LVDS clock

divider and fanout buffer. The device is designed for the frequency

division and signal fanout of high-frequency, low phase-noise clocks.

The 8T74S208A-01 is characterized to operate from a 2.5V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the 8T74S208A-01 ideal for those clock

distribution applications demanding well-defined performance and

repeatability. The integrated input termination resistors make

interfacing to the reference source easy and reduce passive

component count. Each output can be individually enabled or

disabled in the high-impedance state controlled by a I²C register. On

power-up, all outputs are disabled.

One differential input reference clock

Differential pair can accept the following differential input levels:

LVDS, LVPECL, CML

Integrated input termination resistors

Eight LVDS outputs

Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

Maximum input clock frequency: 1GHz

LVCMOS interface levels for the control inputs

Individual output enabled/ disabled by I²C interface

Output skew: 45ps (maximum)

Output rise/fall times: 370ps (maximum)

Low additive phase jitter, RMS: 96fs (typical)

Full 2.5V supply voltage

Outputs disable at power up

Lead-free (RoHS 6) 32-Lead VFQFN packaging

-40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

nQ0

31 30 29 28 27 26 25

nQ1

f_REF

ADR1

GND

FSEL0

GND

nQ7

÷1, ÷2,

÷4, ÷8

nIN

nQ2

50

V_T

nQ3

nQ0

8T74S208A-01

Pulldown (2)

FSEL[1:0]

nQ6

nQ4

nQ1

GND

V_DDO

GND

V_DDO

nQ5

Pullup

SDA

I²C

10 11 12 13 14 15 16

Pullup

SCL

nQ6

Pulldown (2)

ADR[1:0]

nQ7

8T74S208A-01

32-Lead VFQFN, 5mm x 5mm x 0.925mm

8T74S208A-01 REVISION 2 08/17/16

12 3 4 5 6 7...19

中文翻译

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与8T74S208A-01相关器件

型号	品牌	获取价格	描述	数据表
8T74S208A-01_16	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208A-01NLGI	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208A-01NLGI8	IDT	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01	IDT	获取价格	2.5 V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01	RENESAS	获取价格	2.5V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01NLGI	IDT	获取价格	2.5 V Differential LVDS Clock Divider and Fanout Buffer
8T74S208C-01NLGI8	IDT	获取价格	2.5 V Differential LVDS Clock Divider and Fanout Buffer
8T79S308	RENESAS	获取价格	1:8 Universal Differential Fanout Buffer
8T79S828I-08	RENESAS	获取价格	1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer
8T79S838-08NLGI	IDT	获取价格	1-to-8 Differential to Universal Output Fanout Buffer

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