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8T73S208A-01NLGI8 PDF预览

8T73S208A-01NLGI8

更新时间: 2024-12-01 01:10:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
24页 438K
描述
2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

8T73S208A-01NLGI8 数据手册

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2.5V, 3.3V Differential LVPECL Clock  
Divider and Buffer  
8T73S208A-01  
REFER TO PCN# N1605-01, Effective Date August 18, 2016  
DATA SHEET  
FOR NEW DESIGNS USE PART NUMBER: 8T73S208B-01NLGI  
General Description  
Features  
One differential input reference clock  
The 8T73S208A-01 is a high-performance differential LVPECL clock  
divider and fanout buffer. The device is designed for the frequency  
division and signal fanout of high-frequency, low phase-noise clocks.  
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V  
power supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the 8T73S208A-01 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. The integrated input termination resistors make  
interfacing to the reference source easy and reduce passive  
component count. Each output can be individually enabled or  
disabled in the high-impedance state controlled by a I2C register. On  
power-up, all outputs are disabled.  
Differential pair can accept the following differential input  
levels: LVDS, LVPECL, CML  
Integrated input termination resistors  
Eight LVPECL outputs  
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8  
Maximum input clock frequency: 1GHz  
LVCMOS interface levels for the control inputs  
Individual output enable/disabled by I2C interface  
Power-up state: all outputs disabled  
Output skew: 60ps (maximum)  
Output rise/fall times: 350ps (maximum)  
Low additive phase jitter, RMS: 182fs (typical)  
Full 2.5V and 3.3V supply voltages  
Lead-free (RoHS 6) 32-Lead VFQFN packaging  
-40°C to 85°C ambient operating temperature  
8T73S208A-01 REVISION 2 05/20/16  
1
©2016 Integrated Device Technology, Inc.  

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