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8T73S208B-01NLGI PDF预览

8T73S208B-01NLGI

更新时间: 2024-12-01 01:14:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
22页 508K
描述
2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer

8T73S208B-01NLGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:VFQFN-32针数:32
Reach Compliance Code:compliant风险等级:2.29
其他特性:ALSO OPERATES AT 3.3 V SUPPLY系列:8T
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):1.23 nsSame Edge Skew-Max(tskwd):0.06 ns
座面最大高度:1 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
Base Number Matches:1

8T73S208B-01NLGI 数据手册

 浏览型号8T73S208B-01NLGI的Datasheet PDF文件第2页浏览型号8T73S208B-01NLGI的Datasheet PDF文件第3页浏览型号8T73S208B-01NLGI的Datasheet PDF文件第4页浏览型号8T73S208B-01NLGI的Datasheet PDF文件第5页浏览型号8T73S208B-01NLGI的Datasheet PDF文件第6页浏览型号8T73S208B-01NLGI的Datasheet PDF文件第7页 
2.5 V, 3.3 V Differential LVPECL Clock  
Divider and Fanout Buffer  
8T73S208B-01  
Datasheet  
General Description  
Features  
The 8T73S208B-01 is a high-performance differential LVPECL clock  
divider and fanout buffer. The device is designed for the frequency  
division and signal fanout of high-frequency, low phase-noise clocks.  
The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V  
power supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the 8T73S208B-01 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. The integrated input termination resistors make  
interfacing to the reference source easy and reduce passive  
component count. Each output can be individually enabled or  
disabled in the high-impedance state controlled by a I2C register. On  
power-up, all outputs are disabled.  
One differential input reference clock  
Differential pair can accept the following differential input  
levels: LVDS, LVPECL, CML  
Integrated input termination resistors  
Eight LVPECL outputs  
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8  
Maximum input clock frequency: 1GHz  
LVCMOS interface levels for the control inputs  
Individual output enable/disabled by I2C interface  
Power-up state: all outputs disabled  
Output skew: 60ps (maximum)  
Output rise/fall times: 350ps (maximum)  
Low additive phase jitter, RMS: 182fs (typical)  
Full 2.5V and 3.3V supply voltages  
Lead-free (RoHS 6) 32-Lead VFQFN packaging  
-40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
Q0  
nQ0  
31 30 29 28 27 26 25  
32  
Q1  
nQ1  
fREF  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
ADR1  
VEE  
FSEL0  
VEE  
IN  
nIN  
÷1, ÷2,  
÷4, ÷8  
Q2  
nQ2  
50  
50  
Q0  
nQ7  
Q7  
VT  
Q3  
nQ3  
nQ0  
Q1  
Pulldown (2)  
FSEL[1:0]  
2
nQ6  
Q6  
Q4  
nQ4  
nQ1  
VEE  
VEE  
Q5  
nQ5  
Pullup  
VCCO  
VCCO  
SDA  
SCL  
I2C  
9
10 11 12 13 14 15 16  
Pullup  
8
Q6  
Pulldown (2)  
nQ6  
ADR[1:0]  
2
Q7  
nQ7  
5mm x 5mm, 32-pin VFQFN  
©2016 Integrated Device Technology, Inc.  
1
April 28, 2016  

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