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8430AY-62T PDF预览

8430AY-62T

更新时间: 2024-11-11 06:33:15
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
23页 828K
描述
500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer

8430AY-62T 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
Is Samacsys:NJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
湿度敏感等级:3端子数量:32
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:500 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Clock Generators
最大压摆率:130 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

8430AY-62T 数据手册

 浏览型号8430AY-62T的Datasheet PDF文件第2页浏览型号8430AY-62T的Datasheet PDF文件第3页浏览型号8430AY-62T的Datasheet PDF文件第4页浏览型号8430AY-62T的Datasheet PDF文件第5页浏览型号8430AY-62T的Datasheet PDF文件第6页浏览型号8430AY-62T的Datasheet PDF文件第7页 
ICS8430-62  
500MHz, Crystal-to-3.3V, 2.5V  
Differential LVPECL Frequency Synthesizer  
DATASHEET  
General Description  
Features  
The ICS8430-62 is a general purpose, dual output  
Crystal-to-3.3V, 2.5V Differential LVPECL High  
Frequency Synthesizer and a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from IDT. The ICS8430-62 has a selectable  
Dual differential 3.3V or 2.5V LVPECL outputs  
S
IC  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
HiPerClockS™  
REF_CLK  
Output frequency range: 20.83MHz to 500MHz  
Crystal input frequency range: 14MHz to 27MHz  
VCO range: 250MHz to 500MHz  
REF_CLK or crystal inputs. The VCO operates at a frequency range  
of 250MHz to 500MHz. The VCO frequency is programmed in steps  
equal to the value of the input reference or crystal frequency. The  
VCO and output frequency can be programmed using the serial or  
parallel interfaces to the configuration logic. Frequency steps as  
small as 1MHz can be achieved using a 16MHz crystal or REF_CLK.  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 35ps (maximum)  
Full 3.3V or 3.3V core/2.5V output supply  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
Pullup  
VCO_SEL  
Pullup  
XTAL_SEL  
Pin Assignment  
Pulldown  
REF_CLK  
0
32 31 30 29 28 27 26 25  
XTAL_IN  
OSC  
1
1
2
3
4
5
6
7
8
M5  
XTAL_OUT  
24  
23  
22  
21  
20  
XTAL_OUT  
M6  
M7  
REF_CLK  
XTAL_SEL  
VCCA  
÷1  
÷1.5  
÷2  
÷3  
÷4  
÷6  
÷8  
÷12  
÷16  
M8  
N0  
S_LOAD  
PLL  
N1  
N2  
S_DATA  
S_CLOCK  
MR  
19  
18  
17  
Phase Detector  
÷M  
VEE  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
0
1
Pulldown  
VCO  
9
10 11 12 13 14 15 16  
MR  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
S_LOAD  
S_DATA  
ICS8430-62  
32 Lead LQFP  
7mm x 7mm x 1.4mm package body  
Configuration  
Interface Logic  
TEST  
S_CLOCK  
nP_LOAD  
Y Package  
Top View  
9
3
M0:M8  
N0:N2  
ICS8430AY-62 REVISION A JULY 2, 2009  
1
©2009 Integrated Device Technology, Inc.  

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