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8430S10BYI-02LFT PDF预览

8430S10BYI-02LFT

更新时间: 2024-02-29 00:50:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
31页 506K
描述
Clock Generator for Cavium Processors

8430S10BYI-02LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PTQFP
包装说明:HTFQFP, TQFP48,.35SQ针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.22
Samacsys Description:TQFP 7 X7 X 1.0- EXPOSED PADJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:133.33 MHz封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装等效代码:TQFP48,.35SQ
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

8430S10BYI-02LFT 数据手册

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Clock Generator for Cavium  
Processors  
8430S10I-02  
Data Sheet  
General Description  
Features  
The 8430S10I-02 is a PLL-based clock generator specifically  
designed for Cavium Networks SoC processors. This high  
performance device is optimized to generate the processor core  
reference clock, the DDR reference clocks, the PCI/PCI-X bus  
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.  
The clock generator offers ultra low-jitter, low-skew clock outputs,  
and edge rates that easily meet the input requirements for the  
CN30XX/CN31XX/CN38XX/CN58XX processors. The output  
frequencies are generated from a 25MHz external input source or an  
external 25MHz parallel resonant crystal. The extended temperature  
range of the 8430S10I-02 supports telecommunication, networking,  
and storage requirements.  
One selectable differential output pair for DDR 533/400/667,  
LVPECL, LVDS interface levels  
Nine LVCMOS/ LVTTL outputs, 20typical output impedance  
Selectable external crystal or differential (single-ended) input  
source  
Crystal oscillator interface designed for 25MHz, parallel resonant  
crystal  
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL  
input levels  
Internal resistor bias on nCLK pin allows the user to drive CLK  
input with external single-ended (LVCMOS/ LVTTL) input levels  
Power output supply modes  
LVDS and LVPECL – full 3.3V  
LVCMOS – full 3.3V or mixed 3.3V core/2.5V output  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Applications  
Systems using Cavium Processors  
CPE Gateway Design  
Home Media Servers  
802.11n AP or Gateway  
Soho Secure Gateway  
Pin Assignment  
Soho SME Gateway  
Wireless Soho and SME VPN Solutions  
Wired and Wireless Network Security  
Web Servers and Exchange Servers  
48 47 46 45 44 43 42 41 40 39 38 37  
VDD  
VDDO_CD  
QC  
1
2
3
4
36  
nOE_D  
GND  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QD0  
nPLL_ SEL  
QD  
1
ICS8430S10I-02  
CORE_SEL  
GND  
5
6
XTAL_IN  
XTAL_ OUT  
nXTAL_ SEL  
7mm x 7m x 1mm  
package body  
GND  
7
& Package  
CLK  
8
nOE_REF  
VDDO_B  
QB0  
Top View  
9
nCLK  
nOE_C  
10  
nOE_B  
GND  
QB1  
11  
12  
VDDO_B  
15 16 17 18 19 20 21 22 23  
13 14  
24  
©2016 Integrated Device Technology, Inc.  
1
October 4, 2016  

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