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8430S10BYI-02LFT PDF预览

8430S10BYI-02LFT

更新时间： 2024-01-05 03:23:10
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
31页 506K
描述
Clock Generator for Cavium Processors

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8430S10BYI-02LFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：PTQFP
包装说明：HTFQFP, TQFP48,.35SQ针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.22
Samacsys Description：TQFP 7 X7 X 1.0- EXPOSED PADJESD-30 代码：S-PQFP-G48
JESD-609代码：e3长度：7 mm
湿度敏感等级：3端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：133.33 MHz封装主体材料：PLASTIC/EPOXY
封装代码：HTFQFP封装等效代码：TQFP48,.35SQ
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：25 MHz认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

8430S10BYI-02LFT 数据手册

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8430S10I-02 Data Sheet  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 13, 23  
VDD  
Power  
Input  
Core supply pins.  
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are  
in high impedance (HI-Z). When logic LOW, the outputs are enabled.  
LVCMOS/LVTTL interface levels.  
2
nOE_D  
Pulldown  
3, 12, 30, 31,  
39, 42, 46  
GND  
Power  
Input  
Input  
Power supply ground.  
PLL bypass. When LOW, PLL is enable. When HIGH, PLL is bypassed.  
LVCMOS/LVTTL interface levels.  
4
nPLL_SEL  
Pulldown  
5,  
6
XTAL_IN,  
XTAL_OUT  
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.  
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when  
HIGH. LVCMOS/LVTTL interface levels.  
7
8
9
nXTAL_SEL  
CLK  
Input  
Input  
Input  
Pulldown  
Pulldown  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
nCLK  
Inverting differential clock input. Internal resistor bias to VDD/2.  
Active LOW output enable for Bank C output. When logic HIGH, the output is in  
high impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL  
interface levels.  
10  
nOE_C  
Input  
Input  
Pulldown  
Pulldown  
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are in  
high impedance (HI-Z). When logic LOW, the outputs are enabled.  
LVCMOS/LVTTL interface levels.  
11  
14  
nOE_B  
nOE_A  
Input  
Input  
Pulldown  
Pulldown  
Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels.  
Selects the SPI PLL clock reference frequency. See Table 3D.  
15,  
16  
SPI_SEL1,  
SPI_SEL0  
17,  
18  
PCI_SEL1,  
PCI_SEL0  
Selects the PCI, PCI-X reference clock output frequency. See Table 3C.  
LVCMOS/LVTTL interface levels.  
Input  
Input  
Pulldown  
Pulldown  
19,  
20  
DDR_SEL1,  
DDR_SEL0  
Selects the DDR reference clock output frequency. See Table 3B.  
LVCMOS/LVTTL interface levels.  
21, 22  
24  
nQA, QA  
VDDA  
Output  
Power  
Power  
Output  
Differential output pair. Selectable between LVPECL and LVDS interface levels.  
Analog supply pin.  
25, 28  
26, 27  
VDDO_B  
QB1, QB0  
Bank B output supply pins. 3.3 V or 2.5V supply.  
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.  
Active LOW output enable. When logic HIGH, the QREF[2:0] outputs are in high  
impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled.  
LVCMOS/ LVTTL interface levels.  
29  
32  
nOE_REF  
Input  
Input  
Pulldown  
Pulldown  
Selects the processor core clock output frequency. The output frequency is 50MHz  
when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL  
interface levels.  
CORE_SEL  
33, 34  
35  
QD1, QD0  
QC  
Output  
Output  
Power  
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.  
Single-end Bank C output. LVCMOS/LVTTL interface levels.  
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.  
36  
VDDO_CD  
Pin descriptions continue on the next page.  
©2016 Integrated Device Technology, Inc.  
3
October 4, 2016  
1234567...31

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